• The KIPS Transactions:PartD
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• v.14D no.7
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• pp.719-726
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• 2007

Recently, NAND flash memory has been used for a storage device in various mobile computing devices such as MP3 players, mobile phones and laptops because of its shock-resistant, low-power consumption, and none-volatile properties. However, due to the very distinct characteristics of flash memory, disk based systems and applications may result in severe performance degradation when directly adopting them on flash memory storage systems. Especially, when a B-tree is constructed, intensive overwrite operations may be caused by record inserting, deleting, and its reorganizing, This could result in severe performance degradation on NAND flash memory. In this paper, we propose an efficient buffer management scheme, called IBSF, which eliminates redundant index units in the index buffer and then delays the time that the index buffer is filled up. Consequently, IBSF significantly reduces the number of write operations to a flash memory when constructing a B-tree. We also show that IBSF yields a better performance on a flash memory by comparing it to the related technique called BFTL through various experiments.

• Journal of Satellite, Information and Communications
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• v.9 no.2
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• pp.69-73
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• 2014

Recent interest in the worldwide energy to increase, and energy savings of the energy for effective operation of the IT technology there is a demand. By using a low-power LED energy efficient energy use worldwide for a variety of studies have been conducted. In Korea, 20-30% of the domestic electricity consumption corresponding to the illumination in order to conserve energy used by various sensors associated with illumination control studies are underway. That is the next generation of energy began to pay attention to the LED light source, LED and Arduino In this paper, an ultrasonic sensor to control and want to maximize the energy efficiency of the management. Paper, the user is directly operating the separate controller that controls the LED light, instead of being recognized through human body detection LED light on / off to control the experiment and study verified. In this paper, we develop an interface that also allows them to maximize the efficiency of energy management and efficiency, accompanied by expansion of commercialization can be achieved.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.285-291
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• 2010

Flash memory has many good features such as small size, shock-resistance, and low power consumption, but the cost of flash memory is still high to substitute for hard disk entirely. Recently, some mobile devices, such as laptops, attempt to use both flash memory and hard disk together for taking advantages of merits of them. However, existing OSs (Operating Systems) are not optimized to use the heterogeneous storage media. This paper presents a new buffer cache management scheme. First, we allocate buffer cache space according to access patterns of block references and the characteristics of storage media. Second, we prefetch data blocks selectively according to the location of them and access patterns of them. Third, we moves destaged data from buffer cache to hard disk or flash memory considering the access patterns of block references. Trace-driven simulation shows that the proposed schemes enhance the buffer cache hit ratio by up to 29.9% and reduce the total I/O elapsed time by up to 49.5%.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.4
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• pp.213-225
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• 2007

Flash memory is widely used as a storage device for potable equipments such as digital cameras, MP3 players and cellular phones because of its characteristics such as its large volume and nonvolatile feature, low power consumption, and good performance. However, a block in flash memories should be erased to write because of its hardware characteristic which is called as erase-before-write architecture. The erase operation is much slower than read or write operations. FTL is used to overcome this problem. We compared the performance of the existing FTL algorithms on Windows-based OS. We have developed a tool called FTL APAT in order to gather I/O patterns of the disk and analyze the performance of the FTL algorithms. It is the log buffer scheme with full associative sector translation(FAST) that the performance is best.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.3
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• pp.111-116
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• 2013

With technology scaling, soft error rate has greatly increased in embedded systems. Due to high performance and low power consumption, VLIW (Very Long Instruction Word) architectures have been widely used in embedded systems and thus many researches have been studied to improve the reliability of a system by duplicating instructions in VLIW architectures. However, existing studies have ignored the feature, called VLES (Variable Length Execution Set), which is adopted in most modern VLIW architectures to reduce code size. In this paper, we propose how to support instruction duplication in VLIW architecture with VLES. Our experimental results demonstrate that a VLIW architecture with VLES shows 64% code size decrement on average at the cost of about 4% additional cell area as compared to the case of a VLIW architecture without VLES when instruction duplication is applied to both architectures. Also, it is shown that the case with VLES does not cause extra execution time compared to the case without VLES.

• The KIPS Transactions:PartA
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• v.15A no.6
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• pp.325-334
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• 2008

Flash memory is widely used as a storage medium for mobile devices such as cell phones, MP3 players, PDA's due to its tiny size, low power consumption and shock resistant characteristics. Additionally, some computer manufacturers try to replace hard-disk drives used in Laptops or personal computers with flash memory. More recently, there are some literatures on developing a flash memory-aware $B^+$-tree index for an efficient key-based search in the flash memory storage system. They focus on minimizing the number of "overwrites" resulting from inserting or deleting a sequence of key values to/from the $B^+$-tree. However, in addition to this factor, the size of a physical page allocated to a node can affect the maintenance cost of the $B^+$-tree. In this paper, with diverse experiments, we compare and analyze the costs of construction and search of the $B^+$-tree and the space requirement on flash memory as the node size increases. We also provide sorting-based or non-sorting-based algorithms to be used when inserting a key value into the node and suggest an header structure of the index node for searching a given key inside it efficiently.

• The KIPS Transactions:PartD
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• v.17D no.6
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• pp.383-394
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• 2010

Flash memory based SSDs are currently being considered as a promising candidate for replacing hard disks due to several superior features such as shorter access time, lower power consumption and better shock resistance. However, SSDs have different characteristics from hard disk such as difference of unit and time for read, write and erase operation and impossibility for over-writing. Because of these reasons, SSDs have disadvantages on hard disk based systems, so FTL(Flash Translation Layer) is designed to increase SSDs' efficiency. In this paper, we propose an advanced logical address mapping method for increasing SSDs' performance, which is named HAMM(Hybrid Address Mapping Method). HAMM addresses drawbacks of previous block-mapping method and super-block-mapping method and takes advantages of them. We experimented our method on our own SSDs simulator. In the experiments, we confirmed that HAMM uses storage area more efficiently than super-block-mapping method, given the same buffer size. In addition, HAMM used smaller memory than block-mapping method to construct mapping table, demonstrating almost same performance.

• The KIPS Transactions:PartD
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• v.17D no.6
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• pp.395-404
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• 2010

Solid-State Disks (SSDs) have been currently considered as a promising candidate to replace hard disks, due to their significantly short access time, low power consumption, and shock resistance. SSDs, however, have drawbacks such that their write throughput and life span are decreased by random-writes, nearly regardless of SSDs controller designs. Previous studies have mostly focused on better designs of SSDs controller and reducing the number of write operations to SSDs. We suggest another method that reallocates data pages that tend to be simultaneously written to contiguous blocks. Our method gathers write operations during a period of time and generates write traces. After transforming each trace to a set of transactions, our method mines frequent itemsets from the transactions and reallocates the pages of the frequent itemsets. In addition, we introduce an algorithm that reallocates the pages of the frequent itemsets with moderate time complexity. Experiments using TPC-C workload demonstrated that our method successfully reduce 6% of total logical block access.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.11
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• pp.419-426
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• 2014

The recent trend of performance increase in the smart mobile devices demands more power consumption and lower batter life time. Among three battery models of mathematical model, electrochemical model and electric model, the Thevenin's equivalent circuit with non-linear function model of SOC in the electrical model is widely used. However, the OCV results have only limited accuracy because of the characteristic shift caused by temperature and age and atypical impedance property that cannot expressed by electrical components. In this paper, the new battery model that improves the accuracy of the existing models is proposed. In the proposed simulator the mathematical model for SOC characteristic is improved and the adjustment for the temperature, the age of battery and atypical electrical characteristics. In the experimental results of predicting of the battery in the static and dynamic state, the proposed simulator shows improved MSE comparing to the results of the existing methods.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.9
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• pp.617-625
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• 2009

NAND flash memory is widely used in embedded systems because of many attractive features, such as small size, light weight, low power consumption and fast access speed. However, it requires garbage collection, which includes erase operations. Erase operation is very slow. Besides, the number of the erase operations allowed to be carried out for each block is limited. The proposed garbage collection method focuses on minimizing the total number of erase operations, the deviation value of each block and the garbage collection time. NAND flash memory consists of pages of three types, such as valid pages, invalid pages and free pages. In order to achieve above goals, we use a page rate to decide when to do garbage collection and to select the target victim block. Additionally, We implement allocating method and group management method. Simulation results show that the proposed policy performs better than Greedy or CAT with the maximum rate at 82% of reduction in the deviation value of erase operation and 75% reduction in garbage collection time.