• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.121-126
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• 2007

This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

• Journal of Convergence for Information Technology
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• v.10 no.5
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• pp.1-7
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• 2020

This paper proposes a link adaptation method for Underwater Internet of Things (IoT), which reduces power consumption of sensor nodes and improves the throughput of network in underwater IoT network. Adaptive Modulation and Coding (AMC) technique is one of link adaptation methods. AMC uses the strong correlation between Signal Noise Rate (SNR) and Bit Error Rate (BER), but it is difficult to apply in underwater IoT as it is. Therefore, we propose the machine learning based AMC technique for underwater environments. The proposed Modulation Coding and Scheme (MCS) prediction model predicts transmission method to achieve target BER value in underwater channel environment. It is realistically difficult to apply the predicted transmission method in real underwater communication in reality. Thus, this paper uses the high accuracy BER prediction model to measure the performance of MCS prediction model. Consequently, the proposed AMC technique confirmed the applicability of machine learning by increase the probability of communication success.

• Journal of the Korea Convergence Society
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• v.9 no.10
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• pp.69-74
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• 2018

IP and SIP public broadcasting systems developed in Korea and abroad are developed in a Windows or Linux server environments and are installed in a server-rack structure, have high power consumption, and are difficult to remotely respond to system failures. In this paper, IoT platform is designed to connect IoT device and gateway to IoT service server by using internet service structure. We also designed a server based on embedded OS that can provide a variety of public safety management services according to the order of the server with built-in call processing and broadcasting function that can handle emergency calls and emergency broadcasts in public places using this structure. This server is interoperable with a variety of SIP-based call and broadcast devices that support the standard SIP and can be integrated with an in-house phone and on-premises system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.1-6
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• 2000

Recently, SrBi$_{2}$Ta$_{2}$ $O_{9}$(SBT) and Pb(Zr,Ti) $O_{3}$(PZT) were much attracted as materials of capacitor for ferroelectric random access memory(FRAM) with higher read/ write speed, lower power consumption and nonvolartility. SBT thin film has appeared as the most prominent fatigue free and low operation voltage. To highly integrate FRAM, SBT thin film has to be etched. A lot of papers have been reported over growth of SBT thin film and its characteristics. However, there are few reports about etching SBT thin film owing to difficult of etching ferroelectric materials. SBT thin film was etched in CF$_{4}$Ar plasma using magnetically enhanced inductively coupled plasma (MEICP) system. In order to investigate the chemical reaction on the etched surface of SBT thin films, X-ray Photoelecton spectrosocpy (XPS) and Secondary ion mass spectroscopy(SIMS) was performed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.46-53
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• 2003

This paper describes a new linear operational transconductance amplifier (OTA) and its application to the 9th-order Bessel filter. To improve the linearity of the OTA, we employ a mobility compensation technique. The combination of the triode and the subthreshold region transistors can compensate the mobility reduction effect and make the OTA with a good linearity. The proposed OTA shows $\pm$0.32% Gm variation over the input range of $\pm$0.8-V. The total harmonic distortion (THD) was lower than -60-㏈. The 9th-order Bessel filter has been designed using a 0.35-${\mu}{\textrm}{m}$ n-well CMOS process under 3.3-V supply voltage. It shows the cutoff frequency of 8-MHz and the power consumption of 65-mW.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.2
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• pp.19-27
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• 1999

This paper propose a contention resolution policy featuring dynamic change of the threshold for the occupancy of the input buffer for an input buffering ATM switching architecture and its hardware implementation strategy. The strategy is provided with the aim of the simple structure that achieves the reduction of the signal path and the power consumption. The threshold is changed dynamically every time slot based both the arrived of cells and the cell service resulting from the contention resolution. The performance on the cell loss of the proposed policy is performed and compared with the conventional policy under the diverse traffic conditions through both the analysis based ont the Markov chain and the simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.49-54
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• 2009

This paper describes implementation of the 1.9GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma }-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.2{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.1{\times}0.4mm^2$. The test results show that there is no special spurs except -63.06dB of the 6MHz reference spurs in the PLL circuitry. There is good phase noise performance like -116.17dBc/Hz in 1MHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.6-14
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• 2011

This paper presents the design of the battery sensor IC for instrumentation of current, voltage using delta-sigma ADC. The proposed circuit consists of programmable gain instrumentation amplifier (PGIA) and second-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a 0.25 ${\mu}m$ CMOS technology. Design circuit show that the modulator achieves 82 dB signal-to-noise ratio (SNR) over a 2 kHz signal bandwidth with an oversampling ratio (OSR) of 256 and differential nonlinearity (DNL) of ${\pm}$ 0.3 LSB, integral nonlinearity (INL) of ${\pm}$ 0.5 LSB. Power consumption is 4.5 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.58-65
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• 2007

As multimedia portable devices become popular, the amount of computation for processing data including video compression has significantly increased. Various researches for low power consumption of the mobile devices and real time processing have been reported. Motion Estimation is responsible for 67% of H.264 encoder complexity. In this research, a new circuit is designed for motion estimation. The new circuit uses motion prediction based on approximate SAD, Alternative Row Scan (ARS), DAU, and FDVS algorithms. Our new method can reduce the amount of computation by 75% when compared to multi-frame motion estimation suggested in JM8.2. Furthermore, optimal number and size of reference frame blocks are determined to reduce computation without affecting the PSNR. The proposed Motion Estimation method has been verified by using the hardware and software Co-Simulation with iPROVE. It can process 30 CIF frames/sec at 50MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.86-90
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• 2007

An efficient sensing scheme applicable to DC-DC converters is proposed. The output voltage of the DC-DC converter is fed back and converted to a current signal at the input terminal of the sensor to decide if it is in the tolerable range. The comparison is accomplished by a current push-pull action. With the embedded reference current in the sensor realized from the reference voltage. The advantages of the scheme lie in the fairly accurate and efficient implementation in terms of power consumption and chip size overhead compared with conventional voltage-mode schemes as the major parameter in converting voltage to current is determined by (W/L) aspect ratio of the core transistors. In this paper, a DC-DC converter of 5V output from battery range of 2.2V${\sim}$3.6V adopting the proposed sensing scheme is implemented in a 0.35um CMOS process to prove the validity of the scheme.