• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7C
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• pp.915-920
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• 2004

In this paper, we propose the new polyphase sequence with the best nonperiodic autocorrelation property in the viewpoint of the merit factors, which are important criteria for a nonperiodic autocorrelation property. We propose the general implementation of a polyphase sequence generator over an integer residue ring by using a linear feedback shift register(LFSR), in addition, we analyze the linear complexities of polyphase sequences based on the proposed implementation method.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.163-170
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• 2007

In this paper, we propose that the polyphase scaler whose performance to that of the bicubic method, has less complexity in hardware structure. In order to get the new information, proposed system is based on the group delay which is one of the digital filter characteristics. The performance of this system is superior to that of bicubic algorithm which is well known. Because the hardware structure is simpler than other image scalers, we can adopt this system for mobile devices easily. The previous polyphase filters make blurring noise which is generated by up-scaling. We replace polyphase filters by boost-up filter to get vivid image. The proposed scaler is verified by Xilinx Virtex2 FPGA and is used as digital Boom in mobile camera phone.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.2
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• pp.65-72
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• 2006

In digital signal processing, the polyphase decomposition of signal has been often used in the implementation of multirate system. Especially, in the design of digital filter and so forth the method in very useful to improve the performance of various algorithms because it provides the multi-channel for paralled processing. Generally, the polyphase-decomposed signals tend to expand the frequency band by including more high frequencies than original signal from decimation for down sampling. This property brings about the significant limitation in the structure or the performance of digital polyphase signal processing system. In this paper we theoretically propose a perfect band compression and reconstruction method for polyphase component signals, then experimentally show its effectiveness through Matlab simulation.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.7
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• pp.610-615
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• 2014

Filterbanks have been widely used in the field of multi-channel signal processing for their simple efficient implementation architectures. Especially, the polyphase DFT(Discrete Fourier Transform) filterbank is the most preferred filterbank for the uniform spaced multi-channel processing due to its simplicity. In frequency hopped communication systems, however, the use of the polyphase DFT filterbank is limited due to its undesirable transient response from hop-to-hop transitions. In this paper, the transient response of polyphase DFT filterbanks in the hop-to-hop transition was analyzed, and the efficient methods to overcome such a problem was proposed. Simulation results showed that the proposed schemes could resolve this issue efficiently.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.238-243
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• 2010

A new implementation method for MPDSAP(Maximally Polyphase Decomposed Subband Affine Projection) adaptive filter is proposed. The affine projection(AP) adaptive filter achieves fast convergence speed, however, its implementation is so expensive because of the matrix inversion for a weight-updating of adaptive filter. The maximally polyphase decomposed subband filtering allows the AP adaptive filter to avoid the matrix inversion, moreover, by using a pipelining technique, the simple subband structured AP is suitable for VLSI implementations concerning throughput, power dissipation and area. Computer simulations are presented to verify the performance of the proposed algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.4
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• pp.789-796
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• 2013

It is known that the detection of hopping signals without any information about hopping duration and hopping frequency is rather difficult. This paper considers the blind detection of hopping signal's information such as hopping duration and hopping frequency from the sampled wideband signals. In order to find hopping information from the wideband signals, multiple narrow-band filters are required in general, which leads to huge implementation complexity. Instead, this paper employs the polyphase DFT(discrete Fourier transform) filterbank to reduce the implementation complexity. This paper propose hopping signal detection algorithm from the polyphase DFT filterbank output. Specifically, based on the binary image processing, the proposed algorithm is developed to decrease the memory size and H/W complexity. The performance of the proposed algorithm is evaluated through the computer simulation and FPGA (field programmable gate array) implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.7
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• pp.1707-1717
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• 1998

Polyphase filtering techniques is used to suppress the narrowband jammer signal such as USDC TDMA overlaying the band occupied by DS-CDMA system. In the proposed jammer suppression, the received signal is separated into 64 subchannels in two stages by polyphase filtering and the location of the narrowband jammer signal is determined by measuring each subchannel power and the contaminated subchannels are simply blocked. The $E_{b}/N_{0}$ 0/ improvement of the CDMA system from jammer suppession was outstanding. The $E_{b}/N_{0}$ degradation in comparison with a performance of no jammer is around 0.8dB in the worst case. The results are also compared with those of linear prediction jammer suppression. The implementation of the ployphase jammer suppression requires great amount of data processing and computation compared to linear predication filter. Thus it is more appropriate to implement with a ASIC rather than WITH several DSPs for user terminals of forward link.

• ETRI Journal
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• v.25 no.5
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• pp.345-355
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• 2003

In this paper, we propose a method for designing a class of M-channel, causal, stable, perfect reconstruction, infinite impulse response (IIR), and parallel uniform discrete Fourier transform (DFT) filter banks. It is based on a previously proposed structure by Martinez et al. [1] for IIR digital filter design for sampling rate reduction. The proposed filter bank has a modular structure and is therefore very well suited for VLSI implementation. Moreover, the current structure is more efficient in terms of computational complexity than the most general IIR DFT filter bank, and this results in a reduced computational complexity by more than 50% in both the critically sampled and oversampled cases. In the polyphase oversampled DFT filter bank case, we get flexible stop-band attenuation, which is also taken care of in the proposed algorithm.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.1-9
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• 1989

This paper deals with the simplification and the conversion time reduction for the 12-channel TDM/FDM transmultiplexing system using the polyphase network and the FDCT. The prototype filter required in the digital polyphase network is designed based on interpolated FIR (IFIR) properites of the IFIR coefficients, the multiplication rate required in its implementaion is shown to be $0.1640{\times}10^6$ multiplications/sec. channel which reduces about 25% of the result obtained in the previous work. The result of computer simulation indicates that the proposed conversion method is valid.

• Journal of the Korea Institute of Military Science and Technology
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• v.24 no.5
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• pp.475-481
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• 2021

The on-board processor of satellite Synthetic Aperture Radar(SAR) digitizes the back-scattered echoes and transmits them to the ground. As satellite SAR image of various operating conditions including broadband and high resolution is required, an enormous amount of SAR data is generated. Decimation filter is used for data compression to improve the transmission efficiency of these data. Decimation filter is implemented with the FIR(Finite Impulse Response) filter and here, the decimation ratio and tap length are constrained by resource requirements of FPGA used for implementation. This paper suggests to use a non-integer ratio decimation filter in order to optimize the data transmission efficiency. Also, it proposes a filter design method that remarkably reduces the resource constraints of the FPGA in-use via applying a polyphase filter structure. The required resources for implementing the proposed filter is analysed in this paper.