• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.801-802
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• 1992

Poly Si TFTs have been fabricated from low temperature annealed a-Si films. I-V and C-V characteristics in the off-state region were measured. Analytical model for the leakage current in the off-state was suggested. In the measurement, capacitance increased abruptly with Increasing gate and drain voltage. This phenomena is attributed to the leakage current.

• Korean Journal of Materials Research
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• v.24 no.9
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• pp.443-450
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• 2014

Amorphous (a-Si) films were epitaxially crystallized on a very thin large-grained poly-Si seed layer by a silicide-enhanced rapid thermal annealing (SERTA) process. The poly-Si seed layer contained a small amount of nickel silicide which can enhance crystallization of the upper layer of the a-Si film at lower temperature. A 5-nm thick poly-Si seed layer was then prepared by the crystallization of an a-Si film using the vapor-induced crystallization process in a $NiCl_2$ environment. After removing surface oxide on the seed layer, a 45-nm thick a-Si film was deposited on the poly-Si seed layer by hot-wire chemical vapor deposition at $200^{\circ}C$. The epitaxial crystallization of the top a-Si layer was performed by the rapid thermal annealing (RTA) process at $730^{\circ}C$ for 5 min in Ar as an ambient atmosphere. Considering the needle-like grains as well as the crystallization temperature of the top layer as produced by the SERTA process, it was thought that the top a-Si layer was epitaxially crystallized with the help of $NiSi_2$ precipitates that originated from the poly-Si seed layer. The crystallinity of the SERTA processed poly-Si thin films was better than the other crystallization process, due to the high-temperature RTA process. The Ni concentration in the poly-Si film fabricated by the SERTA process was reduced to $1{\times}10^{18}cm^{-3}$. The maximum field-effect mobility and substrate swing of the p-channel poly-Si thin-film transistors (TFTs) using the poly-Si film prepared by the SERTA process were $85cm^2/V{\cdot}s$ and 1.23 V/decade at $V_{ds}=-3V$, respectively. The off current was little increased under reverse bias from $1.0{\times}10^{-11}$ A. Our results showed that the SERTA process is a promising technology for high quality poly-Si film, which enables the fabrication of high mobility TFTs. In addition, it is expected that poly-Si TFTs with low leakage current can be fabricated with more precise experiments.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.315-318
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• 1999

We have proposed and fabricated the new bottom-gated polycrystalline silicon (poly-Si) thin film transistor (TFT) with a partial amorphous-Si region by employing the selective laser annealing. The channel layer of the proposed TFTs is composed of poly-Si region in the center and a-Si region in the edge. The TEM image shows that the local a-Si region is successfully fabricated by the effective cut out of the incident laser light in the upper a-Si layer. Our experimental results show that the ON/OFF current ratio is increased significantly by more than three orders in the new poly-Si TFT compared with conventional poly-Si TFT. The leakage current is decreased significantly due to the highly resistive a-Si re TFTs while the ON-series resistance of the local a-Si is reduced significantly due to the considerable inducement of electron carriers by the positive gate bias, so that the ON-current is not decreased much.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.1-5
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• 2009

A new pixel circuit for Active Matrix Organic Light Emitting Diodes (AMOLEDs), based on the polycrystalline silicon thin film transistors (Poly-Si TFTs), was proposed and verified by SMART SPICE simulation. One driving and six switching TFTs and one storage capacitor were used to improve display image uniformity without any additional control signal line. The proposed pixel circuit compensates an inevitable threshold voltage variation of Poly-Si TFTs and also compensates the degradation of OLED at low power supply voltage($V_{DD}$). The simulation results show that the proposed pixel circuit successfully compensates the variation of OLED driving current within 0.8% compared with 20% of the conventional pixel circuit.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.297-300
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• 2005

The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) fabricated using sputter deposited amorphous silicon (a-Si) precursor films are investigated. The a-Si films were deposited on flexible polymer substrates using argon-helium mixture gases to minimize the argon incorporation into the film. The precursor films were then laser annealed by using a XeCl excimer laser and a four-mask-processed poly-Si TFT was fabricated with fully self-aligned top gate structure. The fabricated pMOS TFT showed field-effect mobility of $32.4cm^2/V{\cdot}s$ and on/off ratio of $10^6$.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.696-699
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• 2008

A 10-bit source driver using low temperature poly-silicon(LTPS) TFTs is developed. To reduce the DAC area, the DAC structure including two 5-bit resistor-string DACs and analog buffer, which has analog adder is proposed. The source driver is fabricated using LTPS process and its one channel area is $3,200{\mu}m\;{\times}\;260{\mu}m$. The simulated INL and DNL of output voltages are less than 3 LSB and 1 LSB, respectively.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.274-277
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• 2000

Thin Film Transistor(TFTs) were fabricated from poly-Si crystallized by a two-step annealing process on glass substrates. The combination of low-temperature(500$^{\circ}C$) Metal-Induced Lateral Crystallization(MILC) furnace annealing and high -temperature (700$^{\circ}C$) rapid thermal annealing leads to the improvement of the material quality The TFTs measured with this two-step annealing material exhibit better characteristics than those obtained by using conventional MILC furnace annealing.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.509-512
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• 2006

In this paper, we proposed the novel device and process design to enhance the uniformity of low-temperature poly-Si TFTs fabricated by sequential lateral solidification (SLS). The proposed design schemes can avert the conventional two-shot SLS process-induced issues. Moreover, different design considerations between conventional excimer laser crystallization and the SLS process were also proposed and discussed.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.519-522
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• 2002

In this paper, we analyze the impact of plasma etching process induced device degradation on low temperature poly-Si TFTs. The results indicate the relationship between device degradation and PPID effect during plasma fabrication. The dual-gate structure, which is used to suppress leakage current, is also discussed in this research.

• Proceedings of the Materials Research Society of Korea Conference
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• 1999.11a
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• pp.67-67
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• 1999