• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.5
• /
• pp.550-556
• /
• 2016

Polar codes are one of the most favorable capacity-achieving codes due to their simple structure and low decoding complexity. However, because of the disappointing decoding performance realized using conventional successive cancellation (SC) decoders, polar codes cannot be used directly in practical applications. In contrast to conventional SC decoders, list SC (SCL) decoders with large list sizes (e.g. 32) achieve performances very close to those of maximum-likelihood (ML) decoders. In SCL decoders with large list sizes, however, hardware increase is a severe problem because an SCL decoder with list size L consists of L copies of an SC decoder. In this paper, we present a low-area SCL decoder architecture that applies the proposed merged processing element-sharing (MPES) algorithm. A merged processing element (MPE) is the basic processing unit in SC decoders, and the required number of MPEs is L(N-1) in conventional SCL decoders. Using the proposed algorithm reduces the number of MPEs by about 70% compared with conventional SCL decoders when the list size is larger than 32.

• Journal of IKEEE
• /
• v.22 no.4
• /
• pp.1168-1174
• /
• 2018

For the initial state of NAND flash memories, error-free and single-error cases are dominant due to a good channel environment on memory cells. It is important to deal with such cases, which affects the overall system performance. However, the conventional schemes for polar codes equally decode the codes even for the error-free and single-error cases since they cannot classify and decode separately. In this paper, a new pre-processing scheme for polar codes is proposed so as to improve the overall decoding latency by decoding the frequent error-free and single-error cases. Before the ordinary decoding process, the proposed scheme first decodes the frequent error-free and single-error cases. According to the experimental results, the proposed pre-processing scheme decreases the average decoding latency by 64% compared to the conventional scheme for (1024, 512) polar codes.

• Journal of Semiconductor Engineering
• /
• v.1 no.2
• /
• pp.74-80
• /
• 2020

Due to its superior error correcting performance with affordable hardware complexity, the Polar code becomes one of the most important error correction codes (ECCs) and now intensively examined to check its applicability in various fields. However, Successive Cancellation (SC) decoding that brings the advanced Successive Cancellation List (SCL) decoding suffers from the long latency due to the nature of serial processing limiting the practical implementation. To mitigate this problem, many decoding architectures, mainly divided into pruning and parallel decoding, are presented in previous manuscripts. In this paper, we compare the recent SC decoding architectures and analyze them using a tree structure.

• Journal of IKEEE
• /
• v.24 no.2
• /
• pp.550-558
• /
• 2020

Successive cancellation (SC) decoding that is one of the decoding algorithms for polar codes has long decoding latency and low throughput because of the nature of successive decoding. To reduce the latency and increase the throughput, various decoding structures for polar codes are presented. In this paper, we compare the previous decoding structures and analyze them by dividing into two types, pruning and multi-path decoders. Decoders for applying pruning are representative of SSC (simplified SC), Fast-SSC and redundant-LLR structures, and decoders with multi-path are representative of 2-bit SC and redundant-LLR structures. All the previous structures are compared in terms decoding latency and hardware area, and according to the comparison, the syndrome check based decoder has the lowest latency and redundant-LLR decoder has the highest hardware efficiency.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.18 no.5
• /
• pp.1412-1430
• /
• 2024

The soft cancellation list (SCANL) decoding algorithm for polar codes runs L soft cancellation (SCAN) decoders with different decoding factor graphs. Although it can achieve better decoding performance than SCAN algorithm, it has high latency. In this paper, a fast simplified SCANL (Fast-SSCANL) algorithm that runs L independent Fast-SSCAN decoders is proposed. In Fast-SSCANL decoder, special nodes in each factor graph is identified, and corresponding low-latency decoding approaches for each special node is propose first. Then, syndrome check aided Fast-SSCANL (SC-Fast-SSCANL) algorithm is further put forward. The ordinary nodes satisfied the syndrome check will execute hard decision directly without traversing the factor graph, thereby reducing the decoding latency further. Simulation results show that Fast-SSCANL and SC-Fast-SSCANL algorithms can achieve the same BER performance as the SCANL algorithm with lower latency. Fast-SSCANL algorithm can reduce latency by more than 83% compared with SCANL, and SC-Fast-SSCANL algorithm can reduce more than 85% latency compared with SCANL regardless of code length and code rate.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2012.11a
• /
• pp.64-66
• /
• 2012

본 논문에서는 각기 다른 자료를 지닌 두 송신자가 하나의 수신자에게 릴레이를 거쳐 자료를 전송하는 Ynetwork 시스템에서 Polar code 의 구조적인 특징을 이용해 오류율을 줄여 전송할 수 있는 방법을 제안한다. Polar code 는 부호의 길이 N 이 커짐에 따라 임의의 B-DMC(Binary-Discrete Memoryless Channel)에 대해 채널 용량을 달성할 수 있는 부호이며 반복적인 구조로 인해 부호화와 복호화 복잡도가 낮은 장점을 가진 부호이다. 이러한 성질을 이용해 Y-network 시스템의 릴레이에서 간단한 이진 모듈로 덧셈으로 전체 부호의 길이를 늘려 전송효율을 높일 수 있다.

• Journal of electromagnetic engineering and science
• /
• v.11 no.4
• /
• pp.239-249
• /
• 2011

In this paper, we propose a reliable $8{\times}8$ up-down switching polar relay code based on 3GPP LTE standard, motivated by 3GPP LTE down link, which is 30 bps/Hz for $8{\times}8$ MIMO antennas, and by Arikan's channel polarization for the frequency selective fading (FSF) channels with the generator matrix $Q_8$. In this scheme, a polar encoder and OFDM modulator are implemented sequentially at both the source node and relay nodes, the time reversion and complex conjugation operations are separately implemented at each relay node, and the successive interference cancellation (SIC) decoder, together with the cyclic prefix (CP) removal, is performed at the destination node. Use of the scheme shows that decoding at the relay without any delay is not required, which results in a lower complexity. The numerical result shows that the system coded by polar codes has better performance than currently used designs.

• ETRI Journal
• /
• v.46 no.3
• /
• pp.485-500
• /
• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.8
• /
• pp.3-14
• /
• 2013

We demonstrate a fashion of quantum channel combining and splitting, called polar quantum channel coding, to generate a quantum bit (qubit) sequence that achieves the symmetric capacity for any given binary input discrete quantum channels. The present capacity is achievable subject to input of arbitrary qubits with equal probability. The polarizing quantum channels can be well-conditioned for quantum error-correction coding, which transmits partially quantum data through some channels at rate one with the symmetric capacity near one but at rate zero through others.

• ETRI Journal
• /
• v.43 no.2
• /
• pp.184-196
• /
• 2021

The research domain of underwater communication has garnered much interest among researchers exploring underwater activities. The underwater environment differs from the terrestrial setting. Some of the main challenges in underwater communication are limited bandwidth, low data rate, propagation delay, and high bit error rate (BER). As such, this study assessed the underwater acoustic (UWA) aspect and explored the expression of error performance based on t-distribution noise. Filter orthogonal frequency-division multiplexing refers to a new waveform candidate that has been adopted in UWA, along with turbo and polar codes. The empirical outcomes demonstrated that the noise did not adhere to Gaussian distribution, whereas the simulation results revealed that the filter applied in orthogonal frequency-division multiplexing could significantly suppress out-of-band emission. Additionally, the performance of the turbo code was superior to that of the polar code by 2 dB at BER 10-3.