• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.309-312
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• 2002

Triode field emitters with planar-carbon-nanopaticle (CNP) cathodes were successfully fabricated using the conventional photolithography and the hotfilament chemical vapor deposition. Electron emission from a CNP triode emitter with a 12-${\mu}m$-diameter gate hole started at the gate voltage of 45 V, and the anode current reached the level of ${\sim}120$ nA at the gate voltage of 60 V, respectively. For the quantitative analysis of the Fowler-Nordheim (F-N) type emission from a CNP triode emitter, we carried out 2dimensional numerical calculation of electrostatic potential using the finite element method. As it turned out, a radial variation of electric field was very important to account for the emission from a planar emitting layer. By assuming the graphitic work function of 5 eV for CNPs, we were able to extract a consistent set of F-N parameters, together with the radial position of emitting sites.

• Electrical & Electronic Materials
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• v.7 no.5
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• pp.376-382
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• 1994

In this study we developed a program(DEVSIM) to simulate the two dimensional distribution of the electrostatic potential and the electric field of the arbitrary structure consisting of GaAs/AlGaAs semiconductor and metal as well as dielectric. By the comparision of the electric field distribution of GaAs MESFETs with the various recess gates we proposed a suitable device structure to improve the breakdown characteristics of MESFET. According to the results of simulation the breakdown characteristics were improved as the thickness of the active epitaxial layer was decreased. And the planar structure, which had the highly doped layer under the drain for the ohmic contact, was the worst because the highly doped layer prevented the space charge layer below the gate from extending to the drain, which produced the narrow spaced distribution of the electrostatic potential contours resulting in the high electric field near the drain end. Instead of the planar structure with the highly doped drain the recess gate structure having the highly doped epitaxial drain layer show the better breakdown characteristics by allowing the extention of the space charge layer to the drain. Especially, the structure in which the part of the drain epitaxial layer near the gate show the more improvement of the breakdown characteristics.

• Journal of IKEEE
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• v.27 no.4
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• pp.630-635
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• 2023

SiC is replacing the position of silicon in the power semiconductor field due to its superior resistance to adverse conditions such as high temperature and high voltage compared to silicon, which occupies the majority of existing industrial fields. In this paper, the gate of 4H-SiC Planar MOSFET, one of the power semiconductor devices, was formed with aluminium to make the contrast and parameter values consistent with polycrystalline Si gate, and the threshold voltage, breakdown voltage, and IV characteristics were studied by varying the channel doping concentration of SiC MOSFET.

• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.222-226
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• 2016

This paper investigated the trench process, unified field limit ring, and other products for the development of a 500 V-level unified trench gate power MOSFET. The optimal base chemistry for the device was found to be SF₆. In SEM analysis, the step process of the trench gate and field limit ring showed outstanding process results. After finalizing device design, its electrical characteristics were compared and contrasted with those of a planar device. It was shown that, although both devices maintained a breakdown voltage of 500 V, the Vth and on-state voltage drop characteristics were better than those of the planar type.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.2
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• pp.96-99
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• 2012

We fabricated fully depleted (FD) SOI-based 1T-DRAM cells with planar channel or recessed channel and the electrical characteristics were investigated. In particular, the dependence of memory operating mode on the channel structure of 1T-DRAM cells was evaluated. As a result, the gate induced drain leakage current (GIDL) mode showed a better memory property for planar type 1T-DRAM. On the other hand, the impact ionization (II) mode is more effective for recessed type.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.8
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• pp.490-495
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• 2015

This paper was proposed the theoretical research and optimal design 3,000 V IGBT for using electrical automotive, high speed train and first power conversion. To obtaining 3,000 V breakdown voltage, the design parameters was showed $160{\Omega}{\cdot}cm$ resistivity and $430{\mu}m$ drift length. And to maintain 5 V threshold voltage, we obtained $6.5{\times}10^{13}cm^{-2}$ p-base dose. We confirmed $24{\mu}m$ cell pitch for maintain optimal on state voltage drop and thermal characteristics. This 3,000 V IGBT was replaced to thyristor devices using first power conversion and high speed train, presently.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1991.10a
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• pp.205-209
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• 1991

The conventional modeling equations for planar MOSFET can not be directly used for zero or minus junction depth concave MOSFET. In this paper, we suggest a new model which can simulate the electrical characteristics of concave MOSFET. The threshold voltage modeling was achieved using the charge sharing method considering the relative difference of source and drain depletion widths. To analyze the ID-VDS characteristics, the conventional expressions for planar MOSFET were employed with the electrical channel length as an effective channel length and the channel length modulation factor as ${\alpha}$ΔL. By comparing the proposed model with experimental results, we could get reasonably similar curves and we proposed a concave MOSFET conditiion which shows no short channel effect of threshold voltage(V${\gamma}$).

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.651-654
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• 2002

We carried out 2-dimensional numerical calculations of electrostatic potential for triode field emitters with planar cathodes using the finite element method. As it turned out, the conventional triode structure with a planar cathode suffered from large gate current and wide spreading of emitted electrons. To circumvent these shortcomings, we proposed a new triode structure. By simply inserting a conducting layer of proper thickness on top of the cathode layer, we were able to modify the electric field distribution on the cathode surface so that low gate current and electron-focusing effect were achieved, simultaneously.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.97-97
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• 2013

We present a comprehensive study on the integration of h-BN with silicon MOSFET. Temperature dependent mobility modeling is used to discern the effects of top-gate dielectric on carrier transport and identify limiting factors of the system. The result indicates that coulomb scattering and surface roughness scattering are the dominant scattering mechanisms for silicon MOSFETs at relatively low temperature. Interposing a layer of h-BN between $SiO_2$ and Si effectively weakens coulomb scattering by separating carriers in the silicon inversion layer from the charged centers as 2-dimensional h-BN is relatively inert and is expected to be free of dangling bonds or surface charge traps owing to the strong, in-plane, ionic bonding of the planar hexagonal lattice structure, thus leading to a significant improvement in mobility relative to undecorated system. Furthermore, the atomically planar surface of h-BN also suppresses surface roughness scattering in this Si MOSFET system, resulting in a monotonously increasing mobility curve along with gate voltage, which is different from the traditional one with a extremum in a certain voltage. Alternatively, high-k dielectrics can lead to enhanced transport properties through dielectric screening. Modeling indicates that we can achieve even higher mobility by using h-BN decorated $HfO_2$ as gate dielectric in silicon MOSFETs instead of h-BN decorated $SiO_2$.

• Journal of IKEEE
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• v.17 no.3
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• pp.360-364
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• 2013

The maximum breakdown voltage's characteristic within the Super Junction MOSFET structure comes from N-Drift and P-Pillar's charge balance. By developing P-Pillar from Planar MOSFET, it was confirmed that the breakdown voltage is improved through charge balance, and by setting the gate voltage at 10V, the characteristic comparisons of Planar MOSFET and Super Junction MOSFET are shown in picture 6. The results show that it had the same breakdown voltage as Planar MOSFET which increased temperature resistance by 87.4% at $.019{\Omega}cm^2$ which shows that by the temperature resistance increasing, the power module's power dissipation improved.