• Journal of information and communication convergence engineering
• /
• v.8 no.5
• /
• pp.570-574
• /
• 2010

A thinning algorithm changes a binary fingerprint image to one pixel width. A thinning stage occupies 40% cycle of 32-bit RISC microprocessor system for a fingerprint identification algorithm. Hardware block processing is more effective than software one in speed, because a thinning algorithm is iteration of simple instructions. This paper describes an effective hardware scheme for thinning stage processing using the Verilog-HDL in $160\times192$ Pixel Array. The ZS algorithm was applied for a thinning stage. The hardware scheme was designed and simulated in RTL. The logic was also synthesized by XST in FPGA environment. Experimental results show the performance of the proposed scheme.

• Proceedings of the IEEK Conference
• /
• summer
• /
• pp.82-85
• /
• 2004

This paper proposes an advanced circuit for the capacitive type fingerprint sensor signal processing and an effective isolation structure for minimizing an electrostatic discharge(ESD) influence and for removing a signal coupling noise of each sensor pixel. The proposed detection circuit increases the voltage difference between a ridge and valley about $80\%$ more than old circuit. The test chip is composed of $160\;\times\;192$ array sensing cells $(9,913\times11,666\;um^2).$ The sensor plate area is $58\;\times\;58\;um^2$ and the pitch is 60um. The image resolution is 423 dpi. The chip was fabricated on a 0.35um standard CMOS process. It successfully captured a high-quality fingerprint image and performed the registration and identification processing. The sensing and authentication time is 1 sec(.) with the average power consumption of 10 mW at 3.0V. The reveal ESD tolerance is obtained at the value of 4.5 kV.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.12 no.5
• /
• pp.2273-2286
• /
• 2018

This paper describes transformations between elemental image arrays and a RGBD image for three-dimensional integral imaging and transmitting systems. Two transformations are introduced and analyzed in the proposed method. Normally, a RGBD image is utilized in efficient 3D data transmission although 3D imaging and display is restricted. Thus, a pixel-to-pixel mapping is required to obtain an elemental image array from a RGBD image. However, transformations and their analysis have little attention in computational integral imaging and transmission. Thus, in this paper, we introduce two different mapping methods that are called as the forward and backward mapping methods. Also, two mappings are analyzed and compared in terms of complexity and visual quality. In addition, a special condition, named as the hole-free condition in this paper, is proposed to understand the methods analytically. To verify our analysis, we carry out experiments for test images and the results indicate that the proposed methods and their analysis work in terms of the computational cost and visual quality.

• Proceedings of the IEEK Conference
• /
• 2007.07a
• /
• pp.383-384
• /
• 2007

In this paper, we propose the new and simple method for sub-pixel block search algorithm by only using integer-pixel for motion estimation and compensation. In many papers, the fast search block match algorithms based on TSS have been proposed. However, these methods could be achieved a little reduction of the computational complexity. All of searching points by 1/4-pixel have own predicted integer-pixel SAD array. Therefor, if we know initial nine SAD values by integer, which is on the searching area of the reference frame, then we can find optimal searching point by 1/4-pixel, directly.

• Proceedings of the IEEK Conference
• /
• 2000.06d
• /
• pp.242-245
• /
• 2000

In this paper, we present a color interpolation technique based on artificial neural networks for a single-chip CCD (charge-coupled device) camera with a Bayer color filter array (CFA). Single-chip digital cameras use a color filter array and an interpolation method in order to regenerate high quality color images from sparsely sampled images. We applied 3-layer feedforward neural networks in order to interpolate missing pixel from surrounding pixels. And we compared the proposed method with conventional interpolation methods such as the proposed interpolation algorithm based on neural networks provides a better performance than the conventional interpolation algorithms.

• Journal of radiological science and technology
• /
• v.14 no.1
• /
• pp.61-72
• /
• 1991

In this paper, the rotating plate method extracting signal and reconstructing original image was proposed. The rotating methode has cell detector array each of which has used in the medical diagnosis X-ray photography. The major problem using the simple horizontal moving or non-moving methode is the size and number of detector cells which have the considerable affection on the sharpness and resolution of the reconstructed image. Secondary, the estimated pixel values of non-detected real points which are placed between detector cells will be the distorted pixels in the reconstructed image. Therefore, the proposed rotating plate method has the exact distribution on the uncertain pixels which were reconstructed by conventional methods to solve there problems. And then, the image using the rotated plate's cell out put signal was reconstructed on the computer simulation. The method will rotated the detector array plate to solve the reconstruction from the detector size and number of conventional methods. The result of simulation has estimated the original pixel position and 81 pixel/mm resolution which the reconsiderlation of the detector's moving orientation, the proposed method has 25 pixel/mm resolution. These results have been represented by 3-D computer graphics.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.32B no.1
• /
• pp.30-38
• /
• 1995

In this paper, we propose an efficient architecture for motion estimation processor which performs one of essential functions in moving picture coding algorithms. Simple control mechanism of data flow in register array which stores pixel data, parallel processing of pixel data and pipelining scheme in arithmetic umit allow this architecture to process a 352*288 pixel image at the frame rate of 30fs, which is compatable with CCITT standard H.261.

• Proceedings of the KIEE Conference
• /
• 2000.07c
• /
• pp.1745-1747
• /
• 2000

TFT-LCD simulator, PDAST(Pixel Design Array Simulation Tool) could simulate the effect of the variation on the pixel characteristics. Since feed-through voltage in TFT-LCD can be a serious problem to pixel voltage characteristics, it should be compensated. It is applicable to various kinds of TFT-LCDs and can be used to calculate the spontaneous part of common electrode voltage accurately. Also, PDAST can estimate pixel voltage according to various inversion methods. It allows high-speed calculation and the information obtained from this study could be utilized to design the larger area and finer image quality panel.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07b
• /
• pp.873-877
• /
• 2005

Recent developments in Dual Select Diode (DSD) AMLCD technology are described. They include a novel array design and drive method with shared select lines, which leads to higher aperture ratio and a further reduction of module cost. A Color-On-Array DSD process and pixel layout compatible with In-Plane-Switching is also proposed.

• The KIPS Transactions:PartA
• /
• v.9A no.2
• /
• pp.259-266
• /
• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.