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http://dx.doi.org/10.3745/KIPSTA.2002.9A.2.259

A Study on the Pixel-Parallel Usage Processing Using the Format Converter  

Kim, Hyeon-Gi (Keukdong College)
Lee, Cheon-Hui (Dept.of Electronics Engineering, Cheongju University)
Publication Information
The KIPS Transactions:PartA / v.9A, no.2, 2002 , pp. 259-266 More about this Journal
Abstract
In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.
Keywords
Parallel Processing; format Converter; Image Processing;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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1 F. P. Herrmann and C. G. Sodini, 'A 256-elements Associative Parallel Processing,' Symp, VLSI Circuits : Dig. Tech. Papers, pp.99-100, June, 1994
2 Yong-Hui Lee, 'A Study on the Data Retention Time Improvement for High Density & High Performance DRAM,' Doctor's thesis, Chongju University, August, 2001
3 F. P. Herrmann and C. G. Sodini, 'A Dynamic Associative Processor for Machine Vision Applications,' IEEE Micro., Vol.12, No.3, pp.31-41, June, 1992   DOI   ScienceOn
4 Dinesh Bhatia, 'Field Programmable Gate Arrays-a Cheaper Way of Customizing Product Prototypes,' IEEE Potentials, 1994   DOI   ScienceOn
5 Jeffery C. Gealow, Frederick P. Herrmann, Lawrence T. Hsu, and Charles G. Sodini, 'System Design for Pixel-parallel Image Processing,' IEEE Trans. on VLSI systems, pp.32-41, Mar., 1996   DOI   ScienceOn
6 D. Bursky, 'Programmable Array Mix FPGA and ASIC Blocks,' Electronic Design, pp.69-74, Oct., 1996
7 김현기, 이용희, 이천희, '포맷 변환기를 이용한 화소 병렬 영상처리시스템에 관한 연구', 한국정보처리학회 추계학술발표논문집, 제8권 제2호, pp.645-648, October, 2001   과학기술학회마을
8 Jonathan Rose, 'Abbas El Gamal, and Alberto Sangiovanni-Vincentelli,' 'Architecture of Field-Programmable Gate Arraysm' Proc. of the IEEE, Vol.81, No.7, pp.1013-1029, July, 1993   DOI   ScienceOn
9 Xilinx, 'The Programmable Logic Data Book,' 1994