• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.10-17
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• 2011

As the data path of the processor widens and the depth of the pipeline deepens, the number of required registers increases. Consequently, careful attention must be paid to the design of clocked storage elements like latches and flipflops as they have a significant bearing on the overall performance of a synchronous VLSI circuit. As technology is also scaling down, noise immunity is becoming an important factor. In this paper, we present a new flipflop which has an improved noise immunity when compared to the hybrid latch flipflop and the conditional precharge flipflop. Simulation results in 65nm CMOS technology with 1.2V supply voltage are used to demonstrate the effectiveness of the proposed flipflop structure.

• Journal of Mechanical Science and Technology
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• v.17 no.12
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• pp.1835-1843
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• 2003

This paper introduces the development of the caliper system for a geometry PIG (Pipeline Inspection Gauge). The objective of the caliper system is to detect and measure dents, wrinkles, and ovalities affect the pipe structural integrity. The developed caliper system consists of a finger arm, an anisotropic permanent magnet, a back yoke, pins, pinholes and a linear hall effect sensor. The angle displacement of the finger arm is measured by the change of the magnetic field in sensing module. Therefore the sensitivity of the caliper system mainly depends on the magnitude of the magnetic field inside the sensing module. In this research, the ring shaped anisotropic permanent magnet and linear hall effect sensors were used to produce and measure the magnetic field. The structure of the permanent magnet, the back yoke and pinhole positions were optimized that the magnitude of the magnetic field range between a high of 0.1020 Tesla and a low of zero by using three dimensional nonlinear finite element methods. A simulator was fabricated to prove the effectiveness of the developed caliper system and the computational scheme using the finite element method. The experimental results show that the developed caliper system is quite efficient for the geometry PIG with good performance.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.109-118
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• 1998

This paper presents an ASIC implementation of video encoder which converts either digital RGB or YCbCr to S-video(Y/C) and composite video signal. The video timing signal of this encoder includes horizontal sync., vertical sync. signal and blanking, and this encoder supports field identification signal which is convenient for video editing. The encoder has been designed in the 4 stages pipeline structure to assure the stable operation of each submodule. The proposed encoder requires only 20K gates ,which is a 40% reduction in hardware compared with [13]. The designed encoder was fabricated in $0.65{\mu}m$ SOG triple metal CMOS technology. Chip size is $3.7478mm {\times} 4.4678mm$ including PAD, gate counts is 19,468 and dissipated power is 0.9W.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.12
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• pp.10-19
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• 2001

In this paper, we propose an effective but simple multi-rate parallel interference canceller(PIC) for the international mobile telecommunications-2000(IMT-2000) 3rd generation partnership project (3GPP) system. For effective multi-rate processing, we define the basic block as one symbol period of the dedicated physical control channel(DPCCH) having the lowest data rate and common to all users. Then, decision and interference cancellation are performed at every basic block. For an asynchronous channel, we propose an advance removal scheme that removes in advance multiple access interference(MAI) due to the next blockof other users with shorter delay. Introducing a pipeline structure at a sample base, we can implement efficiently the PIC using the advance removal scheme with a minimum hardware and no extra computations. Through computer simulations, we analyze the bit error rate(BER) performance of the proposed PIC with respect to signal-to-noise ratio(SNR) and the number of users.

• Korean Journal of Veterinary Service
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• v.17 no.3
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• pp.208-226
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• 1994

From January to December 1993, 3,385 bulk milk samples were collected from 293 herds in Inchon area. Standard plate counts(SPC) and somatic cell counts(SCC) were performed by the method of milk collection, the situation of raising management and monthly. The results obtained are summarized as follows : 1, Annual average SPC and SCC were respectively 638,000 cfu /mm and 647,000 cells /mm. SPC showed an abrupt decrease from January-1,088,000 cfu /mm to December-279,000 cfu /mm, but SCC showed a slow change from January-1,017,000 cells /mm to December -673,000 cells /mm 2. Variation on milk quality(annual average SPC) was shown a wide difference between everyday collection-575,000 cfu /mm and every other day collection-1,243,000 cfu /mm ac-cording to frequency of milk collection from dairy farms. However, there was a little difference In SCC. 3. In the raising scale, average SPC were the lowest in 16~25mi1king cows, and average SCC were the lowest in above 25milking cows. 4. According to types of milking machine, average SPC and SCC of dairy farms that are equipped with pipeline system were respectively 361,000 cfu /mm and 591,000 cells /mm. Those of dairy farms with bucket system were 549,000 cfu /me and 559,000 cells /mm. 5. In the types of management, average SPC an SCC of dairy farms with hired herdsman were 288,000 cfu /mm and 559,000 cells /mm. Those of dairy farms with self-management were 526,000 cfu /mm and 568,000 cells /mm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.41-50
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• 2010

In this paper, an area-efficient symbol detector is proposed for MIMO communication systems with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode for MIMO transmission technique, and shows the optimal maximum likelihood (ML) performance. Also, by sharing the hardware block with multi-stage pipeline structure and using the complex multiplier based on polar-coordinate，the complexity of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in hardware description language (HDL) and implemented with Xilinx Virtex-5 FPGA. With the proposed architecture, the number of logic slices for the proposed symbol detection is 52490 and the number of DSP48s (dedicated multiplier) is 52, which are reduced by 35.3% and 85.3%, respectively, compared with the conventional architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.865-870
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• 2006

The cellular neural networks have shown a vast computing power for the image processing in spite of the simplicity of its structure. However, it is impossible to implement the CNN hardware which would require the same enormous amount of cells as that of the pixels involved in the practical large image. In this parer, the $5\times5$ CNN hardware and the pre post processor which can be used for processing the real large image with a time-multiplexing scheme are implemented. The implemented $5\times5$ CNN hardware and pre post processor is applied to the edge detection of $256\times256$ lena image to evaluate the performance. The total number of block. By the time-multiplexing process is about 4,000 blocks and to control pulses are needed to perform the pipelined operation or the each block. By the experimental resorts, the implemented $5\times5$ CNN hardware and pre post processor can be used to the real large image processing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.289-292
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• 2008

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of OpenRISC processor and a clock gating algorithm using ODC (Observability Don't Care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC processor using the proposed algorithm is improved about 8.9% and dynamic power of the processor using samsung $0.18{\mu}m$ technology library is reduced by 13.9%.

• Journal of IKEEE
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• v.24 no.3
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• pp.783-790
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• 2020

In this paper, the human detecting radar system for indoor security applications is proposed, and its FPGA-based implementation results are presented. In order to minimize the complexity and memory requirements of the computation, the top half of the spectrogram was used to extract features, excluding the feature extraction techniques that require complex computation, feature extraction techniques were proposed considering classification performance and complexity. In addition, memory requirements were minimized by designing a pipeline structure without storing the entire spectrogram. Experiments on human, dog and robot cleaners were conducted for classification, and 96.2% accuracy performance was confirmed. The proposed system was implemented using Verilog-HDL, and we confirmed that a low-area design using 1140 logics and 6.5 Kb of memory was possible.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.830-833
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• 2007

In this paper, we implemented a $17{\times}17b$ binary digital multiplier using radix-4 Booth;s algorithmand proposed an efficient testing methodology for the full-custom design. A two-stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. Several chips were fabricated using LG Semicon 0.6-um 3-Metal N-well CMOS technology. We did fault simulations efficiently using the proposed test method resulting in the reduction of the number of faulty nodes by 88%. The chip contains 9115 transistors and the core area occupies $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.