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An Implementation of the $5\times5$ CNN Hardware and the Pre.Post Processor  

Kim Seung-Soo (LG 이노텍)
Jeon Heung-Woo (금오공과대학교 전자공학부)
Abstract
The cellular neural networks have shown a vast computing power for the image processing in spite of the simplicity of its structure. However, it is impossible to implement the CNN hardware which would require the same enormous amount of cells as that of the pixels involved in the practical large image. In this parer, the $5\times5$ CNN hardware and the pre post processor which can be used for processing the real large image with a time-multiplexing scheme are implemented. The implemented $5\times5$ CNN hardware and pre post processor is applied to the edge detection of $256\times256$ lena image to evaluate the performance. The total number of block. By the time-multiplexing process is about 4,000 blocks and to control pulses are needed to perform the pipelined operation or the each block. By the experimental resorts, the implemented $5\times5$ CNN hardware and pre post processor can be used to the real large image processing.
Keywords
CNN; Time-multiplexing; Pre.Post processor; OTA; Pipeline;
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