• Safety and Health at Work
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• 제2권3호
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• pp.210-217
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• 2011

Objectives: The purpose of this study was to measure the concentration of volatile organic compound (VOC)s originated from the chemicals used and/or derived from the original parental chemicals in the photolithography processes of semiconductor manufacturing factories. Methods: A total of four photolithography processes in 4 Fabs at three different semiconductor manufacturing factories in Korea were selected for this study. This study investigated the types of chemicals used and generated during the photolithography process of each Fab, and the concentration levels of VOCs for each Fab. Results: A variety of organic compounds such as ketone, alcohol, and acetate compounds as well as aromatic compounds were used as solvents and developing agents in the processes. Also, the generation of by-products, such as toluene and phenol, was identified through a thermal decomposition experiment performed on a photoresist. The VOC concentration levels in the processes were lower than 5% of the threshold limit value (TLV)s. However, the air contaminated with chemical substances generated during the processes was re-circulated through the ventilation system, thereby affecting the airborne VOC concentrations in the photolithography processes. Conclusion: Tens of organic compounds were being used in the photolithography processes, though the types of chemical used varied with the factory. Also, by-products, such as aromatic compounds, could be generated during photoresist patterning by exposure to light. Although the airborne VOC concentrations resulting from the processes were lower than 5% of the TLVs, employees still could be exposed directly or indirectly to various types of VOCs.

• International Journal of Precision Engineering and Manufacturing
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• 제9권1호
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• pp.12-18
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• 2008

This paper describes two run-to-run controllers, a nonlinear multiple exponential-weight moving-average (NMEWMA) controller and a dynamic model-tuning minimum-variance (DMTMV) controller, for photolithography processes. The relationships between the input recipes (exposure dose and focus) and output variables (critical dimensions) were formed using an experimental design method, and the photolithography process model was built using a multiple regression analysis. Both the NMEWMA and DMTMV controllers could update the process model and obtain the optimal recipes for the next run. Quantified improvements were obtained from simulations and real photolithography processes.

• 한국산학기술학회논문지
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• 제13권8호
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• pp.3319-3325
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• 2012

본 논문은 반도체 포토장비의 이산 이벤트 시뮬레이터인 TrackSim의 개발에 관한 것이다. TrackSim은 포토 장비의 시뮬레이션 엔진과 사용하기 쉬운 사용자 환경을 포함하는 시뮬레이터로, 다양한 프로세스 모듈의 구성 및 운영 방법을 효율적으로 평가, 검증, 스케쥴링할 수 있는 3차원 시뮬레이션 환경을 제공한다. TrackSim은 반도체 산업에서 많이 사용되는 이산 사건 시뮬레이션 소프트웨어인 AutoMod를 기반으로 개발되어 시뮬레이션 신뢰성이 보장되며, AutoMod로 개발된 반도체 제조라인 시뮬레이션 모델 속에 함께 연동하여 사용이 가능하다는 특징이 있다.

• 전기학회논문지
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• 제57권1호
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• pp.137-141
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• 2008

Biochip, which implements bioanalytical process on a tiny surface, is one of candidates for medical diagnosis, drug screening, and molecular sensing. In general, a type of biochip based on microfluidics is composed of microcomponents including microchannel, pump, and valve, which require complicated processes. In this study, gray-scale photolithography(GSPL) was applied to fabricate a biochip with multiple layers. A mould for casting PDMS(polydimethylsiloxane) channel, was fabricated using GSPL. A gray-photomask was prepared by printing gray patterns on a high-quality glossy paper followed by photoreducing by 10:1 onto the photo-film. The formation of multiple layers was studied according to the change of gray level of pattern and the developing time. A biochip composed of a weir(multiple layer structure) and a reaction chamber in a single microchannel was fabricated in a glass plate. Finally, we investigated the application of biochip to antigen-antibody reaction by packing the microbead coated with antibody.

• 한국시뮬레이션학회논문지
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• 제14권4호
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• pp.55-68
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• 2005

The advancement in semiconductor technology is leading toward smaller critical dimension designs and larger wafer manufactures. Due to such phenomena, semiconductor industry is in need of an accurate control of the process. Photolithography is one of the key processes where the pattern of each layer is formed. In this process, precise superposition of the current layer to the previous layer is critical. Therefore overlay parameters of the semiconductor photolithography process is targeted for this research. The complex relationship among the input parameters and the output metrologies is difficult to understand and harder yet to model. Because of the superiority in modeling multi-nonlinear relationships, neural networks is used for the simulator modeling. For training the neural networks, conjugate gradient method is employed. An experiment is performed to evaluate the performance among the proposed neural network simulator, stepwise regression model, and the currently practiced prediction model from the test site.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.318-321
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• 2005

FIB (Focused ion Beam) milling on a 500-nm-thick silicon nitride membrane was studied in order to fabricate a high-resolution shadow mask, or called a nanostencil. The silicon nitride membrane was fabricated by MEMS processes of LPCVD, photolithography, ICP etching and bulk silicon etching. The apertures made by FIB milling and normal photolithography were compared. The square metal pattern deposited through FIB milled shadow mask showed 6 times smaller comer radius than the case of photolithography. The results show high resolution patterning could be achieved by local deposition through FIB milled shadow-mask.

• 한국재료학회지
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• 제20권8호
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• pp.423-428
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• 2010

This study shows the effects of deionized (DI) rinse and oxide HF wet etch processes on silicon substrate during a photolithography process. We found a fail at the wafer center after DI rinse step, called Si pits, during the fabrication of a complementary metal-oxide-semiconductor (CMOS) device. We tried to find out the mechanism of the Si pits by using the silicon wafer on CMOS fabrication and analyzing the effects of the friction charge induced by the DI rinsing. The key parameters of this experiment were revolution per minute (rpm) and time. An incubation time of above 10 sec was observed for the formation of Si pits and the rinsing time was more effective than rpm on the formation of the Si pits. The formation mechanism of the Si pits and optimized rinsing process parameters were investigated by measuring the charging level using a plasma density monitor. The DI rinse could affect the oxide substrate by a friction charging phenomenon on the photolithography process. Si pits were found to be formed on the micro structural defective site on the Si substrate under acceleration by developed and accumulated charges during DI rinsing. The optimum process conditions of DI rinse time and rpm could be established through a systematic study of various rinsing conditions.

• 한국분말재료학회지
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• 제30권2호
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• pp.156-168
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• 2023

The semiconductor industry faces physical limitations due to its top-down manufacturing processes. High cost of EUV equipment, time loss during tens or hundreds of photolithography steps, overlay, etch process errors, and contamination issues owing to photolithography still exist and may become more serious with the miniaturization of semiconductor devices. Therefore, a bottom-up approach is required to overcome these issues. The key technology that enables bottom-up semiconductor manufacturing is area-selective atomic layer deposition (ASALD). Here, various ASALD processes for elemental metals, such as Co, Cu, Ir, Ni, Pt, and Ru, are reviewed. Surface treatments using chemical species, such as self-assembled monolayers and small-molecule inhibitors, to control the hydrophilicity of the surface have been introduced. Finally, we discuss the future applications of metal ASALD processes.

• 한국산업보건학회지
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• 제29권3호
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• pp.310-321
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• 2019

Objectives: The purpose of this study was to investigate types and characteristics of chemical substances used in LCD(Liquid crystal display) panel manufacturing process. Methods: The LCD panel manufacturing process is divided into the fabrication(fab) process and module process. The use of chemical substances by process was investigated at four fab processes and two module processes at two domestic TFT-LCD(Thin film transistor-Liquid crystal display) panel manufacturing sites. Results: LCD panels are manufactured through various unit processes such as sputtering, chemical vapor deposition(CVD), etching, and photolithography, and a range of chemicals are used in each process. Metal target materials including copper, aluminum, and indium tin oxide are used in the sputtering process, and gaseous materials such as phosphine, silane, and chlorine are used in CVD and dry etching processes. Inorganic acids such as hydrofluoric acid, nitric acid and sulfuric acid are used in wet etching process, and photoresist and developer are used in photolithography process. Chemical substances for the alignment of liquid crystal, such as polyimides, liquid crystals, and sealants are used in a liquid crystal process. Adhesives and hardeners for adhesion of driver IC and printed circuit board(PCB) to the LCD panel are used in the module process. Conclusions: LCD panels are produced through dozens of unit processes using various types of chemical substances in clean room facilities. Hazardous substances such as organic solvents, reactive gases, irritants, and toxic substances are used in the manufacturing processes, but periodic workplace monitoring applies only to certain chemical substances by law. Therefore, efforts should be made to minimize worker exposure to chemical substances used in LCD panel manufacturing process.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2000년도 추계학술발표강연 및 논문개요집
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• pp.90-90
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• 2000