• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.06a
• /
• pp.303-303
• /
• 2007

Photo-imageable thick-film lithography technology was developed for the fabrication of embedded passives such as inductors and capacitors. In this study, photo-imageable dielectric and conductor pastes have apoted a negative type. Sodalime glass wafer, alumina substrate and zero-shrinkage LTCC green tapes were used as substrates. In result, The lithographic patterns were designed as lines and spaces for conductor material, or via-holes for ceramic, LTCC, materials. The scattering and reflection of UV-beam on the substrate had negative effects on fine patterning. The patterning performance was varied with the exposing and developing process conditions, and also varied with the substrate materials. Fine resolution of less then $50/50{\mu}m$ in line and space was obtained, which is difficult in screen printing method.

• Journal of the Semiconductor & Display Technology
• /
• v.19 no.3
• /
• pp.12-18
• /
• 2020

In semiconductor manufacturing, defect detection is critical to maintain high yield. Currently, computer vision systems used in semiconductor photo lithography still have adopt to digital image processing algorithm, which often occur inspection faults due to sensitivity to external environment. Thus, we intend to handle this problem by means of using Mask R-CNN instead of digital image processing algorithm. Additionally, Mask R-CNN can be trained with image dataset pre-processed by means of the specific designed digital image filter to extract the enhanced feature map of Convolutional Neural Network (CNN). Our approach converged advantage of digital image processing and instance segmentation with deep learning yields more efficient semiconductor photo lithography inspection system than conventional system.

• Design & Manufacturing
• /
• v.12 no.1
• /
• pp.47-51
• /
• 2018

As the IT industry rapidly progresses, the functions of electronic devices and display devices are integrated with high density, and the model is changed in a short period of time. To implement the integration technology, a uniform micro-pattern implementation technique to drive and control the product is required. The most important technology for the micro pattern generation is the exposure processing technology. Failure to implement the basic pattern in this process cannot satisfy the demands in the manufacturing field. In addition, the conventional exposure method of the mask method cannot cope with the small-scale production of various types of products, and it is not possible to implement a micro-pattern, so an alternative technology must be secured. In this study, the technology to implement the required micro-pattern in semiconductor processing is presented through the photolithography process and plasma etching.

• Journal of the Korean Society of Manufacturing Technology Engineers
• /
• v.19 no.6
• /
• pp.834-840
• /
• 2010

Photo lithography process is very important technology to fabricate highly integrated micro patterns with high precision for semiconductor and display industries. Up to now, mask type lithography process has been generally used for this purpose; however, it is not efficient for small quantity and/or frequently changing products. Therefore, in order to obtain higher productivity and lower manufacturing cost, the mask type lithography process should be replaced. In this study, a maskless lithography system using the DMD(Digital Micromirror Device) is developed, and the exposure condition and optical properties are analyzed and simulated for a single beam case. From the proposed experimental conditions, required exposure experiments were preformed, and the results were investigated. As a results, 10${\mu}m$ spots can be generated at optimal focal length.

• Journal of the Korean Magnetics Society
• /
• v.17 no.4
• /
• pp.178-181
• /
• 2007

Electron beam lithography has been studied as a next-generation lithography technology instead of photo lithography for ULSI semiconductor devices. In this work, we have made a low-energy electron beam lithography system based on the microcolumn and investigated the dependence of the pattern thickness on the energies and dose concentration of the electron beam. We have also demonstrated the potential of low-energy lithography by achieving 100 nm-$SiO_2$ thin film patterning.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.18 no.5
• /
• pp.674-680
• /
• 2017

Touch Screen Panel (TSP) is a widely used personal handheld device and as a large display apparatus. This study examines micro bump fabrication technology for TSP test process. In the testing process, as TSP is changed, should make a new micro bump for probing and modify the testing program. In this paper we use a maskless lithography system to confirm the potential to fabricatemicro bump to reducecost and manufacturing time. The requiredmaskless lithography system does not use a mask so it can reduce the cost of fabrication and it flexible to cope with changes of micro bump probing. We conducted electro field simulation by pitches of micro bump and designed the lithography pattern image for the maskless lithography process. Then we conducted Photo Resist (PR) patterning process and electro-plating process that are involved in MEMS technology to fabricate micro bump.

• Journal of the Semiconductor & Display Technology
• /
• v.18 no.1
• /
• pp.38-41
• /
• 2019

Proton beam writing is a direct writing lithography technique for semiconductor fabrication process. The advantage of this technique is that the proton beam does not scatter as they travel through the matter and therefore maintain a straight path as they penetrate into the resist. The experiment has been carried out at Accelerator Mass Spectrometry facility. The focused proton beam with the fluence of $100nC/mm^2$ was exposed on the PMMA coated silicon sample to make a pattern on a photo resist. The results show the potential of proton beam writing as an effective way to produce semiconductor fabrication process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.19 no.10
• /
• pp.960-965
• /
• 2006

This research aims to develop the multiple channel electrochemical DNA chip using microfabrication technology. At first, we fabricated a high integration type DNA chip array by lithography technology. Several probe DNAs consisting of thiol group at their 5-end were immobilized on the gold electrodes. Then target DNAs were hybridized and reacted. Cyclic voltammetry showed a difference between target DNA and control DNA in the anodic peak current values. Therefore, it is able to detect a plural genes electrochemically after immobilization of a plural probe DNA and hybridization of non-labeling target DNA on the electrodes simultaneously. It suggested that this DNA chip could recognize the sequence specific genes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.07b
• /
• pp.768-771
• /
• 2003

Nowadays, the study on the ceramic components and modules used in telecommunication system is being performed. Duplexer is the one of the most important components and has the role of dividing Rx and Tx signal. Duplexer including the FBAR is being done vigorously LTCC is used for package like SAW package, duplexer package. In our research, LTCC material is used for FBAR duplexer package and photo-lithography for the fine line phase shifter. The good characteristics, low loss and good isolation, of duplexer is obtained by the fine line phase shifter having high characteristic impedance of stripline.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.84-84
• /
• 2010

In this study, we report on the novel lithographic patterning method to fabricate organic-semiconductor devices based on photo and e-beam lithography with well-known silicon technology. The method is applied to fabricate pentacene-based organic field effect transistors. Owing to their solubility, sub-micron sized patterning of P3HT and PEDOT has been well established via micromolding in capillaries (MIMIC) and inkjet printing techniques. Since the thermally deposited pentacene cannot be dissolved in solvents, other approach was done to fabricate pentacene FETs with a very short channel length (~30nm), or in-plane orientation of pentacene molecules by using nanometer-scale periodic groove patterns as an alignment layer for high-performance pentacene devices. Here, we introduce the atomic layer deposition of $Al_2O_3$ film on pentacene as a passivation layer. $Al_2O_3$ passivation layer on OTFTs has some advantages in preventing the penetration of water and oxygen and obtaining the long-term stability of electrical properties. AZ5214 and ma N-2402 were used as a photo and e-beam resist, respectively. A few micrometer sized lithography patterns were transferred by wet and dry etching processes. Finally, we fabricated sub-micron sized pentacene FETs and measured their electrical characteristics.