• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.76-81
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• 2013

A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.

• Journal of KSNVE
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• v.2 no.2
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• pp.117-123
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• 1992

In the study, the design method of reconstruction filter is studied for synchronized sampling which is necessary for order tracking in rotating machinery. The original data sampled at constant intervals, using fixed anti- aliasing filters, is reconstructed by digital reconstruction filter and is resampled at new sampling times calculated by a suitable shaft angle encoder pulse arrival times in order to synchronize with shaft velocity. In addition to eliminating the tracking synthesizer and filters, this new method has no phase noise due to phase-locked loops.

• Journal of Communications and Networks
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• v.8 no.1
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• pp.8-12
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• 2006

Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute clock signals along synchronous networks in several telecommunication and control applications. Here, we study the two types of masterslave chains: Without clock feedback, i.e., one-way master-slave (OWMS) and with clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.1
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• pp.31-38
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• 2024

The digital phase-locked loop(DPLL) is one of the circuits composed of a digital detector, digital loop filter, voltage-controlled oscillator, and divider as a fundamental circuit, widely used in many fields such as electrical and circuit fields. A state estimator using various mathematical algorithms is used to improve the performance of a digital phase-locked loop. Traditional state estimators have utilized Kalman filters of infinite impulse response state estimators, and digital phase-locked loops based on infinite impulse response state estimators can cause rapid performance degradation in unexpected situations such as inaccuracies in initial values, model errors, and various disturbances. In this paper, we propose a two-layer Frobenius norm-based finite impulse state estimator to design a new digital phase-locked loop. The proposed state estimator uses the estimated state of the first layer to estimate the state of the first layer with the accumulated measurement value. To verify the robust performance of the new finite impulse response state estimator-based digital phase locked-loop, simulations were performed by comparing it with the infinite impulse response state estimator in situations where noise covariance information was inaccurate.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1347-1356
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• 2018

In a three-phase system, three-phase AC signals can be translated into two-phase DC signals through a coordinate transformation. Thus, the PI regulator can realize a zero steady-state error for the DC signals. In the control of a three-phase grid-connected inverter, the phase angle of grid is normally detected by a phase-locked loop (PLL) and takes part in a coordinate transformation. A novel control strategy for a three-phase grid-connected inverter with a frequency-locked loop (FLL) based on coordinate transformation is proposed in this paper. The inverter is controlled as a current supply. The grid angle, which takes part in the coordinate transformation, is replaced by a periodic linear changing angle from $-{\pi}$ to ${\pi}$. The changing angle has the same frequency but a different phase than the grid angle. The frequency of the changing angle tracks the grid frequency by the negative feedback of the reactive power, which forms a FLL. The control strategy applies to non-ideal grids and it is a lot simpler than the control strategies with a PLL that are applied to non-ideal grids. The structure of the FLL is established. The principle and advantages of the proposed control strategy are discussed. The theoretical analysis is confirmed by experimental results.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.1-6
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• 2019

An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1097-1100
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• 1998

In this paper, the PLL(Phase-Locked Loops) for low voltage and high speed operation is described. In other to obtaining above objects, new CMOS circuit technologies have been used in the each block circuit of PLL. It operates with a lock range from 110 up to 700 MHz and has a peak to peak jitter of 50 ps at operating frequency of 250 MHz. It was fabricated in a $0.6\mu\textrm{m}$ CMOS technology and dissipated 45 mW from a single 3.3V.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1233-1236
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• 2003

This paper proposes a phase-locked loop (PLL) that achieves one-cycle lock acquisition by employing the lock-acquisition circuit (LAC). The LAC produces the initial analog voltage ( v$_{c}$ ) that corresponds to the input frequency. When the transfer curve of the LAC matches that of the voltage-controlled oscillator (VCO), one-cycle locking can be possible. By HSPICE simulations, the proposed LAC is proved to be applicable to any kinds of PLL [1][2][3].].

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.2
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• pp.38-50
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• 1982

A new type of digital phase-locked loop (DPLL) called the modified digital Costas loop is proposed and analyzed. The main feature of the proposed loop is that the phase error detector of the loop has linear characteristic. This results from the use of the tan-1 (.) function in the loop. Accordingly, the DPLL can be characterized by a modulo-2$\pi$ linear difference equation. This paper is diveide into two parts. In Part I we describe the proposed system, and analyze the performance of the first-and second-order loops in the absence of noise by the Phase Plane technique. The locking ranges for the DPLL's to achieve exact locking independently of initial conditions have been obtained in closed forms. Also, the false lock and oscillation phenomena occurring under some initial conditions have been considered. These results have been verified by computer simulation. In Part ll we analyze the proposed system in the presence of noise. The steady state probability density function, mean and variance of the phase error have been obtained by solving the Chapman-Kolmogorov equation. These results will be presented in Part ll.