• Title/Summary/Keyword: Phase-Locked PLL

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A Study to Improve the DC Output Waveforms of AFE Three-Phase PWM Rectifiers (AFE 방식 3상 PWM 정류기의 직류 출력파형 개선에 관한 연구)

  • Jeon, Hyeon-Min;Yoon, Kyoung-Kuk;Kim, Jong-Su
    • Journal of the Korean Society of Marine Environment & Safety
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    • v.23 no.6
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    • pp.739-745
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    • 2017
  • Many studies have been conducted to reduce environmental pollution by ships and reduce fuel consumption. As part of this effort, research on power conversion systems through DC distribution systems that link renewable energy with conventional power grids has been pursued as well. The diode rectifiers currently used include many lower harmonics in the input current of the load and distort supply voltage to lower the power quality of the whole system. This distortion of voltage waveforms causes the malfunctions of generators, load devices and inverter pole switching elements, resulting in a large number of switching losses. In this paper, a controller is presented to improve DC output waveforms, the input Power Factor and the THD of an AFE type PWM rectifier used for PLL. DC output voltage waveforms have been improved, and the input Power Factor can now be matched to the unit power factor. In addition, the THD of the input power supply has been proven by simulation to comply with the requirements of IEEE Std514-2014.

A New Decision-Directed Carrier Recovery Algorithm (새로운 결정지향 반송파 복원 알고리즘)

  • 고성찬
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.7A
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    • pp.1028-1035
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    • 1999
  • To increase the throughput of data transmission in burst-mode TDMA communication systems and also to get a good BER performance at the same time, it is essential to rapidly acquire the carrier while keeping the desirable tracking performance. To achieve this goal, in this paper, a new decision-directed carrier recovery algorithm is presented. The proposed scheme does not incorporate the PLL and suppress the Gaussian random process of input noise by the pre-stage low pass filter so as to get both the fast acquisition and a good performance. Through computer simulations, the performance of the scheme is analyzed with respect to the acquisition time and bit error rate. The cycle slip in the proposed scheme is seldom observed at very low SNR environment in contrast to the previous proposed one. Because of this merit, it is not required to do the differential encoding and decoding in the proposed scheme.

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Design of Hysteretic Buck Converter with A Low Output Ripple Voltage and Fixed Switching Frequency in CCM (작은 출력 전압 리플과 연속 전도모드에서 고정된 스위칭 주파수를 가지는 히스테리틱 벅 변환기 설계)

  • Jeong, Tae-Jin;Jo, Yong-Min;Lee, Tae-Heon;Yoon, Kwang Sub
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.6
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    • pp.50-56
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    • 2015
  • An efficient fast response hysteretic buck converter suitable for mobile application is propoesed. The problems of large output ripple and difficulty in using of small power inductor that conventional hysteretic converter has are improved by adding ramp generator. and the changeable switching frequency with load current is fixed by adding a delay time control circuit composed of PLL structure resulting in decrease of EMI noise. The circuits are implemented by using BCDMOS 0.35um 2-polt 4-metal process. Measurement results show that the converter operates with a switching frequency of 1.85MHz when drives 80mA load current. As the converter drives over 170mA load current, the switching frequency is fixed on 2MHz. The converter has output ripple voltage of less 20mV and more than efficiency 85% with 50~500mA laod current condition.

The development of laser doppler vibrometer using DPLL for the detection of ultrasonic vibration (Digital PLL을 이용한 초음파진동 측정용 레이저 도플러 진동계의 개발)

  • 김호성
    • Korean Journal of Optics and Photonics
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    • v.11 no.5
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    • pp.306-311
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    • 2000
  • This paper deals with the development of Laser Doppler Vibrometer (LDV) that can mea~ure the tlequency and amphlude of the ultrasonic vibralion. Hc-Ne laser (632.8 om) is used as a light source, and Michelson interferometer in winch frequency of the objective beam is shIfted by Bragg cell IS adopted The frequency modulated signal centered at 40 MHz flom the PIN diode IS amplified. down-col1vel1ed to 2.5 MHz, filtered and digiLized. The voltage output that is proportional to the velocity of the vibratwg surface is obtawed using digItal PLL. A microprocessor is used to extract the frequcncy aud amplitude of the vibratIOn from the voltage output. It is found that the developed LDV can measure up to 300 kHz vibratIOn and the mlillmUITI measurable amplitude is I nm at 300 kHz. We believe thatlhis LDV can be used to measure the vibratIOn of the heavy electric maclllnery and micro-size structures. tures.

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A 12 mW ADPLL Based G/FSK Transmitter for Smart Utility Network in 0.18 ㎛ CMOS

  • Park, Hyung-Gu;Kim, Hongjin;Lee, Dong-Soo;Yu, Chang-Zhi;Ku, Hyunchul;Lee, Kang-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.4
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    • pp.272-281
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    • 2013
  • This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

Development of Grid Connection Type Inverter for 30kW Wind Power Generation System (30kW급 발전시스템의 계통 연계형 인버터 개발)

  • Hahm, Nyeon-Kun;Kang, Seung-Ook;Kim, Yong-Joo;Han, Kyong-Hee;Ahn, Gyu-Bok;Song, Seung-Ho;Kim, Dong-Yong;Rho, Do-Hwan;Oh, Young-Jin
    • Proceedings of the KIEE Conference
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    • 2002.07b
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    • pp.990-992
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    • 2002
  • 30kW electrical power conversion system is delveloped for the variable speed wind turbine system. In the wind energy conversion system(WECS) a synchronous generator with field current excitation converts the mechanical energy into electrical energy. As the voltage and frequency of generator output vary according to the wind speed, a dc/dc boosting chopper is utilized to maintain constant dc link voltage. Grid connection type PWM inverter supply currents into the utility line by regulating the dc link voltage. The active power is controlled by q-axis current which the reactive power can be controlled by d-axis current reference change. The phase angle of utility voltage is detected using s/w PLL(Phased Locked Loop) in d-q synchronous reference frame. This scheme gives a low cost power solution for variable speed WECS.

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A Study on the Modification of Frequency Detection Position for Frequency Source in HVDC System Using of AC Voltage (AC전압을 이용한 HVDC 시스템의 주파수 신호원 검출위치 변경에 관한 연구)

  • Park, Jong-Kwang;Kim, Chan-Ki;Yang, Byeong-Mo;Jung, Gil-Jo;Han, Byoung-Sung
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.19 no.6
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    • pp.100-108
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    • 2005
  • In this paper deals with the frequency control of the HVDC scheme linking Haenam to Cheju Island. The primary aim of the study is to develop and evaluate a new frequency control that can be employed without having to utilise the existing Synchronous Compensators(Gas Turbines). Transient condition studies are performed utilising the detailed control strategies for the HVDC link, implemented in PSCAD/EMTDC. Study cases are completed involving synchronous compensators trip and load ripping events and study plots presented. It is demonstrated that the existing frequency measurement can be replaced by one derived from the AC network alone, incorporated into a new frequency control algorithm and gives effective frequency control and dynamic performance.

Coherent and Semi-Coherent Correlation Detection of DSSS-FSK Signals for Low-Power/Low-Cost Wireless Communication (저전력, 저가격 무선통신을 위한 DSSS-FSK 신호의 동기 및 반동기 상관 검파)

  • Park Hyung Chul
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.4 s.334
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    • pp.1-6
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    • 2005
  • For the low power and low cost transceivers, direct sequence spread spec01m frequency-shift keying (DSSS-FSK) is proposed. A transmitter of the DSSS-FSK signal can be implemented by a simple direct modulation using the phase locked loop. Since the DSSS-FSK signal has negligible power around the carrier frequency, low cost direct conversion receiver can be used. Optimum coherent and semi-coherent correlation detection methods for the DSSS-FSK signal are proposed and analyzed. Segmented semi-coherent correlation detection method is proposed to improve the bit error rate performance in the large carrier frequency offset.

A Feed-forward Method for Reducing Current Mismatch in Charge Pumps (전하 펌프의 전류 부정합 감소를 위한 피드포워드 방식)

  • Lee, Jae-Hwan;Jeong, Hang-Geun
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.46 no.1
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    • pp.63-67
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    • 2009
  • Current mismatch in a charge pump causes degradation in spectral purity of the phase locked loops(PLLs), such as reference spurs. The current mismatch can be reduced by increasing the output resistance of the charge pump, as in a cascoded output stage. However as the supply voltage is lowered, it is hard to stack transistors. In this paper, a new method for reducing the current mismatch is proposed. The proposed method is based on a feed-forward compensation for the channel length modulation effect of the output stage. The new method has been demonstrated through simulations on typical $0.18{\mu}m$ CMOS circuits.

Grid-tied Power Conditioning System for Battery Energy Storage Composed of 2-stage DC-DC converter (2단 DC-DC 컨버터로 구성된 배터리 에너지저장용 계통연계형 전력변환장치)

  • Park, Ah-Ryeon;Kim, Do-Hyun;Kim, Kyeong-Tae;Han, Byung-Moon;Lee, Jun-Young
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.61 no.12
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    • pp.1848-1856
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    • 2012
  • This paper proposes a new grid-tied power conditioning system for battery energy storage, which is composed of a 2-stage DC-DC converter and a PWM inverter. The 2-stage DC-DC converter is composed of an LLC resonant converter connected in cascade with a 2-quadrant hybrid-switching chopper. The LLC resonant converter operates in constant duty ratio, while the 2-quadrant hybrid-switching chopper operates in variable duty ratio for voltage regulation. The operation of proposed system was verified through theoretical analysis and computer simulations. Based on computer simulations, a hardware prototype was built and tested to confirm the technical feasibility of proposed system. The proposed system could have relatively higher efficiency and smaller size than the existing system.