• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.272-281
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• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.235-240
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• 2006

Ionospheric scintillation induces a rapid change in the amplitude and phase of radio wave signals. This is due to irregularities of electron density in the F-region of the ionosphere. It reduces the accuracy of both pseudorange and carrier phase measurements in GPS/satellite based Augmentation system (SBAS) receivers, and can cause loss of lock on the satellite signal. Scintillation is not as strong at mid-latitude regions such that positioning is not affected as much. Severe effects of scintillation occur mainly in a band approximately 20 degrees on either side of the magnetic equator and sometimes in the polar and auroral regions. Most scintillation occurs for a few hours after sunset during the peak years of the solar cycle. This paper focuses on estimation of the effects of ionospheric scintillation on GPS and SBAS signals using a software receiver. Software receivers have the advantage of flexibility over conventional receivers in examining performance. PC based receivers are especially effective in studying errors such as multipath and ionospheric scintillation. This is because it is possible to analyze IF signal data stored in host PC by the various processing algorithms. A L1 C/A software GPS receiver was developed consisting of a RF front-end module and a signal processing program on the PC. The RF front-end module consists of a down converter and a general purpose device for acquiring data. The signal processing program written in MATLAB implements signal acquisition, tracking, and pseudorange measurements. The receiver achieves standalone positioning with accuracy between 5 and 10 meters in 2drms. Typical phase locked loop (PLL) designs of GPS/SBAS receivers enable them to handle moderate amounts of scintillation. So the effects of ionospheric scintillation was estimated on the performance of GPS L1 C/A and SBAS receivers in terms of degradation of PLL accuracy considering the effect of various noise sources such as thermal noise jitter, ionospheric phase jitter and dynamic stress error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.55-60
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• 2014

For an high speed communication, a 40GHz VCO was implemented using a 0.11um standard CMOS technology. The mm-wave VCO was designed by a LC type using a spiral inductor, and a simplified architecture with buffers and a smart biasing technique were used to get a high performance. The frequency range of the proposed VCO is 34~40GHz which is suitable for mm-Wave communication system. It has an output power of -16dBm and 16% tuning range. And the phase noise is -100.33dBc/Hz at 1MHz offset at 38GHz fundamental frequency. The total power consumption of VCO including PADs is 16.8mW with 1.2V supply voltage. The VCO achieves the FOMT of -183.8dBc/Hz which is better than previous VOCs.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.107-113
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• 2014

A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.990-992
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• 2002

30kW electrical power conversion system is delveloped for the variable speed wind turbine system. In the wind energy conversion system(WECS) a synchronous generator with field current excitation converts the mechanical energy into electrical energy. As the voltage and frequency of generator output vary according to the wind speed, a dc/dc boosting chopper is utilized to maintain constant dc link voltage. Grid connection type PWM inverter supply currents into the utility line by regulating the dc link voltage. The active power is controlled by q-axis current which the reactive power can be controlled by d-axis current reference change. The phase angle of utility voltage is detected using s/w PLL(Phased Locked Loop) in d-q synchronous reference frame. This scheme gives a low cost power solution for variable speed WECS.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.11
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• pp.1640-1646
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• 2013

Conventional power conversion unit that is a major part of the propulsion system has applied GTO thyristor as a switching semiconductor device of main circuit since introduction of the 8200 electric locomotive. But problem that quick maintenance is difficult and its cost is increasing occurs because major components of the power conversion unit are slowly discontinued. To solve these, in this paper, it was analyzed the response characteristic of the propulsion system modeling of the 8200 electric locomotive using IGBT which is applied recently to ensure propulsion control technology. As results of response for a Propulsion system modeling, it show that a power conversion unit is controlled by PLL(Phase-locked loop) and SVPWM(Space Voltage PWM) respectively.

• ETRI Journal
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• v.40 no.2
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• pp.167-179
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• 2018

This paper proposes an IEEE 802.15.4m compliant TV white-space orthogonal frequency-division multiplexing (TVWS)-(OFDM) radio frequency (RF) transceiver that can be adopted in advanced metering infrastructures, universal remote controllers, smart factories, consumer electronics, and other areas. The proposed TVWS-OFDM RF transceiver consists of a receiver, a transmitter, a 25% duty-cycle local oscillator generator, and a delta-sigma fractional-N phase-locked loop. In the TV band from 470 MHz to 698 MHz, the highly linear RF transmitter protects the occupied TV signals, and the high-Q filtering RF receiver is tolerable to in-band interferers as strong as -20 dBm at a 3-MHz offset. The proposed TVWS-OFDM RF transceiver is fabricated using a $0.13-{\mu}m$ CMOS process, and consumes 47 mA in the Tx mode and 35 mA in the Rx mode. The fabricated chip shows a Tx average power of 0 dBm with an error-vector-magnitude of < 3%, and a sensitivity level of -103 dBm with a packet-error-rate of < 3%. Using the implemented TVWS-OFDM modules, a public demonstration of electricity metering was successfully carried out.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.6
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• pp.100-108
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• 2005

In this paper deals with the frequency control of the HVDC scheme linking Haenam to Cheju Island. The primary aim of the study is to develop and evaluate a new frequency control that can be employed without having to utilise the existing Synchronous Compensators(Gas Turbines). Transient condition studies are performed utilising the detailed control strategies for the HVDC link, implemented in PSCAD/EMTDC. Study cases are completed involving synchronous compensators trip and load ripping events and study plots presented. It is demonstrated that the existing frequency measurement can be replaced by one derived from the AC network alone, incorporated into a new frequency control algorithm and gives effective frequency control and dynamic performance.

• Transactions on Electrical and Electronic Materials
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• v.15 no.6
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• pp.309-314
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• 2014

This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias is used for its high current driving capability and stable frequency response. The proposed divider is designed with $0.18-{\mu}m$ CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL) circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In the output frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an input frequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.