• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.110-116
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• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.2
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• pp.109-116
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• 2005

The high performance drives of the slotless Permanent Magnet Brushless DC(PM BLDC) motor can be achieved by the current control, where the currents flow according to the rotor position and the current phase is suitably controlled according to the operational condition. Rotor position information can be provided by Hall-IC or sensorless algorithm. So, the Hall-ICs are set up in this motor to detect the main flux from the rotor. Instead of using three Hall-ICs and encoder, this paper uses only two Hall-ICs for the permanent magnet rotor position and the speed feedback signals, and uses a micro-controller of 16-bit type (80C196KC). Also because of low resolution obtained by using Hall-IC even low-cost and simple structure, to improve the wide range of speed response characteristic more exactly, we propose the rotor position signal synthesizer using PLL circuit based on two Hall-ICs.

• Journal of Power Electronics
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• v.11 no.3
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• pp.360-368
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• 2011

This paper proposes an active frequency with a positive feedback in the d-q frame anti-islanding method suitable for a robust phase-locked loop (PLL) algorithm using the FFT concept. In general, PLL algorithms for grid-connected PV PCS use d-q transformation and controllers to make zero an imaginary part of the transformed voltage vector. In a real grid system, the grid voltage is not ideal. It may be unbalanced, noisy and have many harmonics. For these reasons, the d-q transformed components do not have a pure DC component. The controller tuning of a PLL algorithm is difficult. The proposed PLL algorithm using the FFT concept can use the strong noise cancelation characteristics of a FFT algorithm without a PI controller. Therefore, the proposed PLL algorithm has no gain-tuning of a PI controller, and it is hardly influenced by voltage drops, phase step changes and harmonics. Islanding prediction is a necessary feature of inverter-based photovoltaic (PV) systems in order to meet the stringent standard requirements for interconnection with an electrical grid. Both passive and active anti-islanding methods exist. Typically, active methods modify a given parameter, which also affects the shape and quality of the grid injected current. In this paper, the active anti-islanding algorithm for a grid-connected PV PCS uses positive feedback control in the d-q frame. The proposed PLL and anti-islanding algorithm are implemented for a 250kW PV PCS. This system has four DC/DC converters each with a 25kW power rating. This is only one-third of the total system power. The experimental results show that the proposed PLL, anti-islanding method and topology demonstrate good performance in a 250kW PV PCS.

• Journal of Korea Multimedia Society
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• v.14 no.5
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• pp.614-621
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• 2011

This paper presents design of a wide tuning range digitally controlled oscillator(DCO) for Mobile-DTV applications. DCO is the key element of the ADPLL block that generates oscillation frequencies. We proposed a binary delay chain(BDC) structure, for wide tuning range DCO, modifying conventional fixed delay chain. The proposed structure generates oscillation frequencies by delay cell combination which has a variable delay time of $2^i$ in the range of $0{\leq}i{\leq}n-1$. The BOC structure can reduce the number of delay cells because it make possible to select delay cell and resolution. We simulated the proposed DCO by Cadence's Spectre RF tool in 1.8V chartered $0.18{\mu}m$ CMOS process. The simulation results showed 77MHz~2.07GHz frequency range and 3ps resolution. The phase noise yields -101dBc/Hz@1MHz at Mobile-DTV maximum frequency 1675MHz and the power consumption is 5.87mW. The proposed DCO satisfies Mobile-DTV standards such as ATSC-M/H, DVB-H, ISDB-T, T-DMB.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1224-1234
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• 2019

Hybrid rotor position estimation methods that integrate a fundamental model and high frequency (HF) signal injection are widely used for the wide speed-range sensorless control of interior permanent-magnet synchronous machines (IPMSMs). However, the direct transition of two different schemes may lead to system fluctuations or system instability since two estimated rotor positions based on two different schemes are always unequal due to the effects of parameter variations, system delays and inverter nonlinearities. In order to avoid these problems, a seamless transition strategy to define and construct a virtual q-axis inductance is proposed in this paper. With the proposed seamless transition strategy, an estimated rotor position based on a fundamental model is forced to track that based on HF signal injection before the transition by adjusting the constructed virtual q-axis inductance. Meanwhile, considering that the virtual q-axis inductance changes with rotor position estimation errors, a new observer with a two-phase phase-locked loop (TP-PLL) is developed to accurately obtain the virtual q-axis inductance online. Furthermore, IPMSM sensorless control with maximum torque per ampere (MTPA) operations can be tracked automatically by selecting the proper virtual q-axis inductance. Finally, experimental results obtained from an IPMSM demonstrate the feasibility of the proposed seamless transition strategy.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.126-142
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• 2016

This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.443-451
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• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.