• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1982-1990
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• 1994

We implemented a PLDRO(Phase Locked Dielectric Resonator Oscillator) using the concept of the feedback property of PLL(Phase Locked Loop) for Ku-band(10.95-11.70 GHz). The conventional approaches to a PLDRO design use varactor diode tuning method.. But in theis paper, the PLDRO has the advantage of the frequency sensitivity to changes in the supple voltage of the oscillating device without the frequency-variable part by varactor diode voltage-control. and uses a SPD(Sampling Phase Detector) for phase-comparision. The PLDRO is composed of the DRO phase-locked to the reference signal of UHF band by using a SPD for high frequency stability and can be available for European FSS(Fixed Satellite Service) at 10.00GHz. The PLDRO generates the output power of 8.67 dBm at 10.00 GHz and has a phase noise of -81 dBc/Hz at 10 kHz offset from carrier. The hamonic and spurious characteristics have -42.33 dBc and -65dBc respectively. This PLDRO has much better frequency stability, lower phase noise, and more economical effect for a satellite system than conventional DRO.

• Proceedings of the Korea Information Processing Society Conference
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• 2024.05a
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• pp.455-456
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• 2024

전력 계통의 Phase 를 제어하기 위해 산업에서 PLL(Phase Locked Loop)제어 시스템을 많이 사용한다. Phase 를 계산함에 있어 계통 전압에 왜곡 발생 시 PLL 을 통한 Phase 에 Noise 가 발생한다. 이를 줄이기 위해, 즉 특정 주파수 대역을 관찰하기 위해 BPF(Band Pass Filter)를 적용하여 PLL 제어기를 설계한 후, Filter 를 적용했을 때와 아닐 때의 위상 차 및 Noise 차이를 분석하여 어떤 경우가 성능적으로 우수한지 확인한다.

• Journal of IKEEE
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• v.17 no.1
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• pp.16-21
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• 2013

Recently, frequency synthesizers are being designed in two ways narrow-band loop or dual-loop for wide-band to reduce the phase noise. However, dual-loop has the disadvantage of center frequency mismatch and requiring an extra loop. In this paper, we propose a new structure that supports a range of 800Mhz ~ 3Ghz with multiple control of the single-loop frequency synthesizer without another loop. The control voltage of the VCO(coarse, fine) will be fixed, and finally the VCO will have a low Kvco. The frequency synthesizer is simulated using UMC $0.11{\mu}m$ process, proposed frequency synthesizer can be used in a variety of applications in the future.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.52-59
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• 1998

New types of PFD (phase-frequency detector) are proposed with reset time and propagation delay reduced. The perfomrance of our proposed PFDs are confirmed by SPICE simulation with 0.8.mu.m CMOS process parameter. As a result of simulation, the reset time of PFDs are 0.32 nsec and 0.030 nsec in capture-process. The proposed PFDs can be used in hihg-speed phase-licked loop (PLL).

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.305-308
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• 2007

본 논문에서는 전력품질 향상용 전력전자기기의 제어에 중요한 정보인 전원의 위상각을 검출하는 기존의 방법들에 대해서 먼저 알아보고, 그 중 불평형한 전원단 전압조건에서도 정확한 위상각을 검출할 수 있는 전차원 상태관측기를 이용한 정상분 전압 추출 PLL(Phase Locked Loop) 방법을 제안한다. 제안된 PLL 방법은 기존의 전역 통과 필터(APF, All Pass Filter)를 이용한 정상분 전압추출기 대신 전차원 상태관측기를 사용함으로써 불평형사고 발생 시 과도상태 응답특성을 개선하였다. 기존의 정상분 전압 추출 PLL 방법과 본 논문에서 제안된 PLL 방법의 성능을 비교하기 위해, 전원단 전압에 불평형 사고 발생시 위상각을 검출하는 모의실험과 실험을 하였고, 이를 통해 기존의 전역 통과 필터를 이용한 정상분 전압 추출 PLL 방법보다 제안된 전차원 상태관측기를 이용한 정상분 전압 추출 PLL 방법의 과도상태 응답특성이 개선됨을 입증하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.46-52
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• 2014

This paper presents a multiple gain controlled digital phase and frequency detector with a fast lock-time. Lock-time of the digital PLL can be significantly reduced by applying proposed adaptive gain control technique. A loop gain of the proposed digital PLL is controlled by three conditions that are very large phase difference between reference and feedback signal, small phase difference and before lock-state, and after lock-state. The simulation result shows that lock-time of the proposed multiple gain controlled digital PLL is 100 times faster than that of the conventional structure with unit gain mode.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.99-106
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• 2012

For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phase-locked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on $V_{ctrl}$ induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 nm CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 MHz output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively.

• Journal of Power Electronics
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• v.15 no.2
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• pp.419-430
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• 2015

Flux estimation is a significant foundation of high-performance control for DC-excited synchronous motor. For almost all flux estimators, such as the flux estimator based on phase locked loop (PLL), DC drift causes fluctuations in flux magnitude. Furthermore, significant dynamic error may be introduced at transient conditions. To overcome these problems, this paper proposes an improved flux estimator for the PLL-based algorithm. Filters based on the generalized integrator are used to avoid flux fluctuation problems caused by the DC drift at the back electromotive force. Programmable low-pass filters are employed to improve the dynamic performance of the flux estimator, and the cutoff frequency of the filter is determined by the dynamic factor. The algorithm is verified by a 960V/1.6MW industrial prototype. Simulation and experimental results show that the proposed estimator can estimate the flux more accurately than the PLL-based algorithm in a cycloconverter-fed DC-excited synchronous machine vector control system.

• Journal of Power Electronics
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• v.13 no.3
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• pp.487-496
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• 2013

The three-phase synchronous reference frame phase-locked loop (SRF-PLL) is widely used for synchronization applications in power systems. In this paper, a new control strategy for three-phase grid-connected LCL inverters without a PLL is presented. According to the new strategy, a current reference can be generated by using the instantaneous power control scheme and the proposed positive-sequence voltage detector. Through theoretical analysis, it is indicated that a high-quality grid current can be produced by introducing the new control strategy. In addition, a kind of independent control for reactive power can be achieved under unbalanced and distorted grid conditions. Finally, the excellent performance of the proposed control strategy is validated by means of simulation and experimental results.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.339-340
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• 2010