• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.191-200
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• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.711-717
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• 2017

This paper proposes an improved sensorless control to estimate the rotor position of an interior permanent magnet synchronous motor. A phase-locked loop (PLL) is used to obtain the phase angle of the grid. The rotor position can be estimated using a PLL based on extended electromotive force (EEMF) because the EEMF contains information about the rotor position. The proposed method can reduce the burden of calculation. Therefore, the control period is decreased. The simulation and experimental results confirm the effectiveness and performance of the proposed method.

• Proceedings of the KSR Conference
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• 2000.05a
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• pp.368-375
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• 2000

For safety reason ATS(Automatic Train Stop) system is being used, which is a kind of communication system with a feedback amplifier and a transformer on the train and wayside coils. The coils are highly resonant LC circuits, also have very high Q(Quality) factors. The Q factors of wayside ATS coils are to be maintained high enough for the amplifier to operate reliably. In this paper a novel Q measurement system is proposed. The system measures the resonant frequency and the bandwidth of the ATS coils, by controlling the phase difference between the transformer and the coil using digital PLL(Phase Locked Loop). The overall configuration and algorithms of the proposed system and the digital PLL control schemes are presented in details. The experimental waveforms are shown to verify the system performances.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.479-481
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• 2006

This paper describes a 2.5V, 320MHz low-noise and low-power Phase Locked Loop(PLL) using a noise-rejected Voltage Controlled ring Oscillator(VCO) fabricated in a TSMC 0.25um CMOS technology. In order to improve the power consumption and oscillation frequency of the PLL, The VCO consist of three-stage fully differential delay cells that can obtain the characteristic of high speed, low power and low phase noise. The VCO operates at 7MHz -670MHz. The oscillator consumes l.58mA from a 320MHz frequency and 2.5V supply. When the PLL with fully-differential ring VCO is locked 320MHz, the jitter and phase noise measured 26ps (rms), 157ps (p-p) and -97.09dB at 100kHz offset. We introduce and analysis the conditions in which ring VCO can oscillate for low-power operation.

• Journal of the Korean Solar Energy Society
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• v.29 no.5
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• pp.65-72
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• 2009

The new method is proposed to improve high speed detection of grid voltage phase and magnitude during a voltage dip due to a grid faults. Usually, A LPF(Low Pass Filter) is used in the feedback loop of PLL (Phase Locked Loop) system because the measured grid voltage contains harmonic distortions and sensor noises. so, a new design method of the loop gain of the PI -type controller in the PLL system is proposed with the consideration of the dynamics of the LPF. As a result, a better transient response can be obtained with the proposed design method. The LPF frequency and PI controller gain are designed in coordination according to the steady state and dynamic performance requirement. This paper shows the feasibility and the usefulness of the proposed methods through the computer simulation and the lab-scale experiments.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.77-84
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• 2000

In this paper, we modelized the multipath fading to Nakagami-m distribution fading channel which can be applied to the extended mobile communication channel environment. We assumed that the phase difference with reference signal happened in the received signal and in the receiver PLL(Phase Locked Loop) is the phase error. To correct the error we propose new RAKE receiver using PLL. In addition, we analyze the performance of DS/SS(Direct Sequence/spread Spectrum) system according to the gain of PLL,$\gamma_n$, the number of RAKE receiver branch L and MIP(Multipath Intensity Profile)'s exponential decay $\delta$. As a result, when the proposed RAKE receiver L Is increased and the $\delta$ is decreased the performance of the system gets better. Futhermore when PLL gain was 30dB, phase is identified. That is when the PLL gain is 30dB, the performance equals with the perfect coherent system's. Therefore, we can correct the phase error by using the proposed RAKE receiver and we proved that the PLL's requested limit gain should be 30dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.9
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• pp.1692-1701
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• 1994

Macromodeling technology is useful to simulate and analyze the performance of new elements and complicated circuits or systems without any changes in today's general simulator, PSPICE. In this paper, Phase Locked Loop(PLL) is designed using macromodeling technique. The PLL macromodel has two basic sub-macromodels of the phase detector and the voltage controlled oscillator(VCO). The PLL macromodel has two open terminals for inserting RC low pass filter. The PLL macromodel is simulated using simulation parameters of LM565CN manufactured in the National company. At a free-running frequency, 2500Hz, upper lock range and lower capture range was 437Hz, 563Hz, respectively. Also, experimental results and simulation results of LM565CN PLL show good agreement.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.181-187
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• 2003

This paper presents an 125MHz, 128-phase phase-locked loop using interpolation technique for digital timing recovery. To reduce the power consumption and chip area, phase interpolation was performed over only selected windows, instead of overall period. Four clocks were used for phase interpolation to avoid the output jitter increase due to the interpolation clock (clock used for phase interpolation) switching. Also, the output clock was fed back to finite-state machine (FSM) where the multiplexer selection signals are generated to eliminate the possible output glitches. The PLL implemented in a $0.25\mu\textrm{m}$ CMOS process and dissipates 80mW at 2.5V supply and occupies $0.84\textrm{mm}^2.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.167-172
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• 2023

A low-noise phase-locked loop(PLL) with three negative feedback loops has been proposed. It is not easy to improve noise characteristics with a conventional PLL. The added negative feedback loops reduce the input voltage magnitude of voltage controlled oscillator which determines the jitter characteristics, enabling the improvement of noise characteristics. Simulation results show that the jitter characteristics are improved as a negative feedback loop is added. In the case of power consumption, it slightly rises by about 10%, but jitter characteristics are improved by about two times. The proposed PLL was simulated with Hspice using a 1.8V 180nm CMOS process.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.224-228
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• 2003

In this paper, for phase lock loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation for modulation signal from high to very low frequency penetrating into the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and blocking the interference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design.