• Journal of Power Electronics
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• 제14권6호
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• pp.1197-1207
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• 2014

Common-mode voltage (CMV) causes overvoltage stress to winding insulation and damages AC motors. CMV with high dv/dt causes leakage currents, which create noise problems for equipment installed near the converter. This study proposes a new pulse-width modulation (PWM) strategy for three-level T-type NPC inverters. This strategy substantially eliminates CMV. The principle for selecting suitable triangle carrier signals for the three-level T-type NPC is described. The proposed method can mitigate the peak value of CMV by 50% compared with the phase disposition pulse-width modulation method. Furthermore, the proposed method exhibits better harmonic spectrum and lower root mean square value for the CMV than those of the reduced-CMV method on the basis of the phase opposition disposition PWM scheme with modulation index higher than 0.5. The proposed modulation can easily be implemented using software without any additional hardware modifications. Both simulation and experimental results demonstrate that the proposed carrier phase-shift PWM method has good output waveform performance and reduces CMV.

• 전기학회논문지
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• 제62권4호
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• pp.502-509
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• 2013

It presents an efficient switching pattern, which expects a reduction of switching losses in a cascaded H-bridge PWM multilevel inverter. By the proposed switching scheme, the lower H-bridge module operates at low frequency of 60[Hz] because it assigns to transfer most load power. The upper H-bridge module operates at high frequency of PWM switching to improve THD of output voltage. The proposed switching pattern applies to cascaded H-bridge multilevel inverter with PD, APOD, bipolar, and unipolar switching methods. By computer-aided simulations, we verify the validity of the proposed switching scheme. Finally, we prove that the proposed PD and APOD switching patterns are better than those of the conventional one in efficiency.

• Journal of Power Electronics
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• 제17권5호
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• pp.1173-1185
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• 2017

In this paper, a new single phase multilevel inverter topology with a single DC source is presented. The proposed topology is developed based on the concepts of the L-Z source inverter and the switched capacitor multilevel inverter. The input voltage to the proposed inverter is boosted by two steps: the first step by an impedance network and the second step by switched capacitor units. Compared to other existing topologies, the presented topology can produce a higher boosted multilevel output voltage while using a smaller number of components. In addition, it provides more flexibility to control boosting factor, size, cost and complexity of the inverter. The proposed inverter possesses all the advantages of the L-Z source inverter and the switched capacitor multilevel inverter like controlling the start-up inrush current and capacitor voltage balancing using a simple switching strategy. The operating principle and general expression for the different parameters of the proposed topology are presented in detail. A phase disposition pulse width modulation strategy has been developed to switch the inverter. The effectiveness of the topology is verified by extensive simulation and experimental studies on a 7-level inverter structure.

• Journal of Power Electronics
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• 제16권4호
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• pp.1316-1323
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• 2016

Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.

• Journal of Power Electronics
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• 제19권4호
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• pp.922-933
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• 2019

The arm inductance (AI) of a modular multilevel converter (MMC) affects both the fault and circulating current magnitudes. In addition, it has an impact on the inverter efficiency and harmonic content. In this study, the AI of a three-phase MMC is optimized in a novel way in terms of DC voltage utilization, harmonics and efficiency. This MMC has 10 submodules (SM) per arm and the power circuit topology of the SM is a half-bridge. The optimum AI is adopted and verified in an MMC that has 100 SMs per arm. Then the phase shift (PS) and phase disposition (PD) pulse width modulation (PWM) methods are investigated for better DC voltage utilization, efficiency and harmonics. It is found that similar performances are obtained for both modulation techniques in terms of DC voltage utilization. However, the total harmonic distortion (THD) of the PS-PWM is found to be 0.02%, which is slightly lower than the THD of the PD-PWM at 0.16%. In efficiency calculations, the switching and conduction losses for all of the semiconductor are considered separately and the minimum efficiency of the 100-SM based MMC is found to be 99.62% for the PS-PWM and 99.64% for the PD-PWM with the optimal value of the AI. Simulation results are verified with an experimental prototype of a 6-SM based MMC.

• Journal of Power Electronics
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• 제15권3호
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• pp.660-669
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• 2015

This paper presents a control scheme with a focus on the combination of phase disposition pulse width modulation (PDPWM) and DC capacitor voltage control for a chopper-cell based modular multilevel converter (MMC) for the purpose of eliminating the time-consuming voltage sorting algorithm and complex voltage balancing regulators. In this paper, the convergence of the DC capacitor voltages within one arm is realized by charging the minimum voltage module and discharging the maximum voltage module during each switching cycle with the assistances of MAX/MIN capacitor voltage detection and PDPWM signals exchanging. The process of voltage balancing control introduces no extra switching commutation, which is helpful in reducing power loss and improving system efficiency. Additionally, the proposed control scheme also possess the merit of a simple executing procedure in application. Simulation and experimental results indicates that the MMC circuit together with the proposed method functions very well in balancing the DC capacitor voltage and improving system efficiency even under transient states.

• Journal of Power Electronics
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• 제12권4호
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• pp.548-558
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• 2012

In this paper, a novel offset-based single-state pulse width modulation (PWM) method for achieving zero common-mode voltage (CMV) and reducing switching losses in multilevel inverters is presented. The specific active switching state of the zero common-mode (ZCM) voltage that approximates the reference voltage can be deduced from the switching state sequence of the reduced CMV phase disposition PWM (CMV PD PWM) method. From the reference leg voltages for the zero common-mode voltage, an N-to-2-level transformation defines a virtual two-level inverter and the corresponding nominal leg voltage references. The commutation process of the reduced CMV PD PWM method in a multilevel inverter and its outputs can be simply followed in a nominal switching time diagram for the virtual inverter. The characteristics of the reduced CMV PD PWM and the single-state PWM for zero common-mode voltage are analyzed in detail in this paper. The theoretical analysis of the proposed PWM method is verified by experimental results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 추계학술대회 논문집
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• pp.9-10
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• 2016

최근 급속한 산업 발달로 인하여 기존의 수 MW급 대용량 인버터가 산업용 팬, 컴프레서, 고속 철도 시스템 등 여러 분야에 사용되면서 이와 관련된 대용량 인버터 연구가 활발히 진행 중이다. 이런 대용량 인버터는 고효율과 직병렬의 구성된 전력용반도체 소자를 동시다발적으로 제어되어야하기 때문에 멀티레벨 인버터의 구조가 가장 적합하다. Cascaded H-bridge 멀티레벨 인버터는 커패시터와 다이오드를 사용하지 않고 스위치만으로 구성하며, 필터를 따로 구성하지 않아도 정현파와 유사하게 전압을 출력할 수 있다. 이로 인해 고주파 감소 및 각 셀을 직렬로 연결하여 입력전압보다 높은 출력전압을 얻을 수 있다. 또한, 스위칭 방법에 따라 동일한 Cascaded H-bridge 멀티레벨인버터 토폴로지에서도 각 THD와 온도에 따른 손실이 달라질 수 있다. Cascaded H-bridge 멀티레벨 인버터에서 이용하는 스위칭 방식은 첫 번째로 유니폴라 방식을 기본으로 한 Phase-shift가 있다. 이는 180도 위상차를 갖는 2개의 레퍼런스 파형과 위상천이가 된 캐리어 파형의 비교로 PWM (Pulse Width Modulation) 을 수행한다. 두 번째 방식으로는 Level-shift가 있다. 이는 캐리어 파형을 IPD (In-Phase Disposition) 방식으로 수직적으로 대역폭이 연속적이게 나열하여 레퍼런스 파형과 비교하는 PWM방식이다. 본 논문에서는 Phase-shift와 Level-shift 방식에 따른 Cascaded H-bridge 인버터와 NPC (Neutral Point Clamped) 인버터를 결합한 토폴로지에서의 온도에 따른 손실을 분석하고, 시뮬레이션을 통하여 비교 분석하였다.