• Title/Summary/Keyword: Phase Margin

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Analysis and Design of the Interface Inductor and the DC Side Capacitor in a STATCOM with Phase and Amplitude Control Considering the Stability of the System

  • Zhao, Guopeng;Han, Minxiao;Liu, Jinjun
    • Journal of Power Electronics
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    • v.12 no.1
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    • pp.193-200
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    • 2012
  • Previous publications regarding the design and specifications of the interface inductor and the DC side capacitor for a STATCOM usually deal with the interface inductor and the DC side capacitor only. They seldom pay attention to the influences of the interface inductor and capacitor on the performance of a STATCOM system. In this paper a detailed analysis of influence of the interface inductor and the DC side capacitor on a STATCOM system and the corresponding design considerations is presented. Phase and amplitude control is considered as the control strategy for the STATCOM. First, a model of a STATCOM system is carried out. Second, through frequency domain methods, such as transfer functions and Bode plots, the influence of the interface inductor and the DC side capacitor on the stability and filtering characteristics of the STATCOM are extensively investigated. Third, according to this analysis, the design considerations based on the phase margin for the interface inductor and the DC side capacitor are discussed, which leads to parameters that are different from those of the traditional design.

Verification for the design limit margin of the power device using the HALT reliability test

  • Chang, YuShin
    • Journal of the Korea Society of Computer and Information
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    • v.23 no.11
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    • pp.67-74
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    • 2018
  • The verification for the design limit margin of the power device for the information communication and surveillance systems using HALT(Highly Accelerated Life Test) reliability test is described. The HALT reliability test performs with a step stress method which change condition until the marginal step in a design and development phase. The HALT test methods are the low temperature(cold) step stress test, the high temperature(hot) step stress test, the thermal shock cyclic stess test, and the high temperature destruct limit(hot DL) step stress test. The power device is checked the operating performance during the test. In this paper, the HALT was performed to find out the design limit margin of the power device.

New Optimal Tuning Method of IMC-PID for SI/SO Systems (단일 입출력 시스템에 대한 IMC-PID의 새로운 최적 동조법)

  • Kim, Chang-Hyun;Lim, Dong-Kyun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.05a
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    • pp.213-217
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    • 2008
  • In this paper, a new design method for IMC-PID that adds a phase scaling factor of system identifications to the standard IMC-PID controller as a control parameter is proposed. Based on analytically derived frequency properties such as gain, phase margin and maximum magnitude of sensitivity function, this tuning rule is an optimal control method determining the optimum values of controlling factors to minimize the cost function, integral error criterion of the step response in time domain, in the constraints of design parameters to guarantee qualified frequency design specifications. The proposed controller improves existing single-parameter design methods of IMC-PID in the inflexibility problem to be able to consider various design specifications. Its effectiveness is examined by a simulation example, where a comparison of the performances obtained with the proposed tuning rule and with other common tuning rules is shown.

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An Optimum Tuning for IMC-PID Controller (IMC-PID 제어기의 최적 동조)

  • Park, Jong-Su;Lim, Dong-Kyun;Suh, Byung-Suhl
    • Proceedings of the KIEE Conference
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    • 2005.10b
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    • pp.167-169
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    • 2005
  • This paper proposes an optimum tuning which improves the tuning effect of IMC-PID and guarantees the performance and robustness of controller system by considering gain margin, phase margin, sensitivity functions and integral square error(ISE) for IMC-PID controller.

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Robust design of SISO digital PI and PID predictor controllers (Robust한 단 입출력 PI 및 PID 예측 제어기 설계)

  • 전병균;전기준
    • 제어로봇시스템학회:학술대회논문집
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    • 1986.10a
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    • pp.362-366
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    • 1986
  • Using simple linear prediction algorithm a design procedure of robust PI and PID controllers for SISO system, usually called 'PID predictor controllers, is developed. The design procedure is able to properly adjust gain margin and phase margin and control coefficients are selected in frequency domain. The performance of the PID predictor controller is superior to that of the normal PID controller in terms of robustness in design and disturbance rejection.

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An Optimum Tuning for IMC-PID Controller (IMC-PID 제어기의 최적 동조)

  • Park, Jong-Su;Lim, Dong-Kyun;Suh, Byung-Suhl
    • Proceedings of the KAIS Fall Conference
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    • 2006.05a
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    • pp.344-347
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    • 2006
  • This paper proposes an optimum tuning which improves the tuning effect of IMC-PID and guarantees the performance and robustness of controller system by considering gain margin, phase margin, sensitivity functions and integral square error(ISE) for IMC-PID controller.

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LTR properties for output-delayed systems (출력 시간 지연 시스템의 루우프 복구특성)

  • 이상정;홍석민
    • 제어로봇시스템학회:학술대회논문집
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    • 1993.10a
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    • pp.161-167
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    • 1993
  • This paper presents robustness properties of the Kalman Filter ad the associated LQG/LTR method for linear time-invariant systems having delays in both the state and output. A circle condition relating to the return difference matrix associated with the Kalman filter is derived. Using this circle condition, it is shown that the Kalman filter guarantees(1/2, .inf.) gain margin and .+-.60.deg. phase margin, which are the same as those for nondelay systems. However, it is shown that, even for minimum phase plants, the LQG/LTR method can not recover the target loop transfer function. Instead, an upper bound on the recovery error is obtained using an upper bound of the solution of the Kalman filter Riccati equations. Finally, some dual properties between output-delated system and input-delayed systems are exploited.

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The performance degradation of CMOS differential amplifiers due to hot carrier effects (Hot carrier 현상에 의한 CMOS 차동 증폭기의 성능 저하)

  • 박현진;유종근;정운달;박종태
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.34D no.7
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    • pp.23-29
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    • 1997
  • The performance degradation of CMOS differential amplifiers due to hot carrier effect has been measured and analyzed. Two-state CMOS amplifiers whose input transistors are PMOSFETs were designed and fabriacted using the ISRC CMOS 1.5.mu.m process. It was observed after the amplifier was hot-carrier stressed that the small-signal voltage gain and the input offset voltage increased and the phase margin decreased. The performance variation results from the increase of the transconductances and gate capacitances of the PMOSFETs used as input transistors in the differential input stage and the output stage and also resulted from the decrease of their output conductances. After long-term stress, the amplifier became unstable. The reason might be that its phase margin was reduced due to hot carrier effect.

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The Stabilized Flyback Converter Design for Lighting Control System (경관조명용 플라이백 컨버터의 안정화 설계)

  • Lim, Seong-Jin;Kim, Chang-Sun;You, Jin-Ho;Cheon, Seung-Hwan
    • Proceedings of the KIPE Conference
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    • 2010.07a
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    • pp.9-10
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    • 2010
  • The lighting control power circuits should be designed in stable region according to the environment. A stable circuit is analyzed using ac equivalent circuits. The flyback converter with wide input voltage ranges is suitable for lighting control system. It is designed optimally for stability. The specifications are that the input voltage is 90V-230V, the output power is 12V/2.5A. The stability analysis is established using PSM(Phase Sensitive Multimeter) in experiment. As a result, it is confirmed that the gain margin and the phase margin are in stable area. The validity of the experimental measurement is verified.

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