• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.649-659
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• 2003

OFDM/FH communication system Is widely used in the wireless communication for the large capacity and high-speed data transmission. However, phase noise and PAPR (peak-to-average power ratio) are the serious problems causing performance impairment. In this paper, PLL (phase locked loop) frequency synthesizer with high switching speed is used for the phase noise model. SSPA and TWTA are considered for the nonlinear HPA model. Under these conditions and by approximating $e^{j{\phi}[m]}$ into $1 + j{\phi}[m]-\frac{1}{2}{\phi}^2[m]$ for the phase noise nonlinear approximation, SINR (signal-to-interference-noise-ratio) with nonlinear HPA and phase noise is derived in the OFDM/FH system. The bit error probabilities (BER) are found by computer simulation method and semi-analytical method. The simulation results closely match with the semi-analytical results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.3
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• pp.205-210
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• 2013

This paper presents a novel hall sensor fault detection and fault-tolerant control method for a high-speed permanent magnet synchronous motor (PMSM) drive system. A phase locked loop (PLL) type position estimator is used with a conventional interpolation based rotor position estimator to reduce position errors due to misalignment of hall sensors. The expected trigger time of hall sensor's output is used for detecting hall sensor fault condition and the PLL type position estimator is reconfigured for fault-tolerant control at the hall sensor fault condition. The proposed method can minimize current ripples during the transition from sensored control using hall sensors to sensorless control. Experimental results have been proposed to prove the validity of the proposed method.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.967-971
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• 2004

The switched reluctance drive is known to provide good adjustable speed characteristics with high efficiency. However, higher torque ripple and lack of the precise speed control are drawbacks. In the paper, a PLL(Phase Locked Loop) technique is adopted to regulate the dwell angle instantaneously. A PLL control technique in conjunction with dynamic dwell angle control scheme has good speed regulation characteristics. The F240 DSP based control system is used to realize this drive system. Test results show that the system has the ability to achieve good dynamic and precise speed control.

• Journal of the Korean Institute of Telematics and Electronics
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• v.9 no.1
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• pp.25-30
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• 1972

Data Communication by sending pulse train and verifying the lock-in of a phase locked loop in receiving end is studied. The noise rejection property inherent to PLL is analysed. By using about six pulses in a train, data transimission rate of 20k bit/sec. in a telephone cable is achieved, thus permitting high speed data communication and an exellent immunity against noise.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.193-196
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• 2001

One of the major reasons for not integrating a VCO on one-chip in a PLL (phase locked loop) system is the large chip-to-chip variation of the VCO (voltage controlled oscillator) center frequency. In this thesis, a simple bias technique is proposed to compensate the process fluctuation. The proposed bias technique is applied to the VCO and it reduces the deviation of the VCO center frequency from 35% to 8 %. With the suggested bias technique, a 400 MHz frequency synthesizer is designed for general purpose. It utilizes a programmable divider for various division ratio. The design methodology provides the possibility of the one-chip solution for a PLL system.

• Journal of Electrical Engineering and Technology
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• v.7 no.3
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• pp.358-365
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• 2012

A new third harmonic injection circuit for light-emitting diode (LED) drivers is proposed to eliminate electrolytic capacitors and thereby extend the lifetime of LED drivers. When a third harmonic current is injected to the input current of the LED driver, the required capacitance of the driver can be reduced. The proposed circuit can control an injection ratio and has simple circuitry. The synchronous third harmonic is generated by a phase locked loop (PLL), a 1/3 counter, and op-amps and applied to a power factor correction circuit. Thus, the storage capacitor can install film capacitors instead of the electrolytic capacitor. The value of storage capacitance can be reduced to 78% compared to an input power factor of 100%. The proposed circuit is applied to the 80W prototype LED driver to experimentally verify the performances.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.7
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• pp.1005-1011
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• 2015

This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.13-22
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• 2001

This paper presents three dimensional structure of RF packages and the improvement effect of its electrical characteristics when implementing RF transceivers. We divided RF modules into several subunits following each subunit function based on the partitioning algorithm which suggests a method of three dimension stacking interconnection, PAA(pad area array) interconnection and stacking of three dimensional RF package structures. 224MHz ITS(Intelligent Transportation System) RF module subdivided into subunits of functional blocks of a receiver(RX), a transmitter(TX), a phase locked loop(PLL) and power(PWR) unit, simultaneously meeting the requirements of impedance characteristic and system stability. Each sub­functional unit has its own frequency region of 224MHz, 21.4MHz, and 450KHz~DC. The signal gain of receiver and transmitter unit showed 18.9㏈, 23.9㏈. PLL and PWR modules also provided stable phase locking, constant voltages which agree with design specifications and maximize their characteristics. The RF module of three dimension stacking structure showed $48cm^3$, 76.9％ reduction in volume and 4.8cm, 28.4％ in net length, 41.8$^{\circ}C$, 37% in maximum operating temperature, respectively. We have found that three dimensional PAA package structure is able to produce high speed, high density, low power characteristics and to improve its functional characteristics by subdividing RF modules according to the subunit function and the operating frequency, and the features of physical volume, electrical characteristics, and thermal conditions compared to two dimensional RF circuit modules.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.247-255
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• 2011

This paper describes a CMOS outphasing transmitter using two wideband phase modulators. The proposed architecture can simplify the overall outphasing transmitter architecture using two-point phase modulation in phase-locked loop, which eliminates the necessity digital-to-analog converters, filters, and mixers. This architecture is verified with a WCDMA signal at 1.65 GHz. The prototype is fabricated in standard 130 nm CMOS technology. The measurement results satisfied the spectrum mask and 4.9% EVM performance.