• Maxillofacial Plastic and Reconstructive Surgery
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• v.16 no.4
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• pp.499-507
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• 1994

The aim of this experiment is to compare the healing process of extraction sockets after immediate implant placement with those using autogenous bone grafts and guided tissue regeneration with Gore-Tex. The first lower premolars and the second premolars of six experimental dogs were extracted and Stryker fin type implants were placed into the extraction sockets immediately after extraction. In the control group, any graft materials were'not used and the dead space around implants was left in itself and covered with only periosteum. In the experimental group A, implants were covered with Gore tex without any bone grafts, and in the experimental group B, the dead space around implants was filled with the bone chips gained from drilling procedure. Each experimental dogs were sacrificed at the 1st, 2nd, 3rd, 6th, and 8th week and the specimens were observed by gross examination, radiological examination, and light microscopic examination. The following results were obtained. 1. Well healed soft tissue and no mobility of the implants were observed in control and two experimental groups. 2. In the radiogical examination, radiopacity around implants had been increased gradually. 3. In the microscopic examination, there were good healing process and active new bone formation in both in the experimental groups, Especially the more amount of new bone formation occurred in the experimental group B using bone chips. 4. Bone chip grafts and guided tissue regeneration (GTR) using Gore-Tex may be one of the successful methods in the immediate implantation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.61-67
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• 2020

In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.355-365
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• 2017

In this paper, we propose the design of a dual-band GPS antenna using in-direct feeding pads. The antenna consists of an upper patch for the GPS L1 band, a lower patch for the GPS L2 band, and two pads on the middle layer for feeding the two radiating patches. A hybrid chip coupler with a phase difference of $90^{\circ}$ is employed at the two feeding ports for achieving a broad circular polarization (CP) bandwidth. The proposed antenna shows bore-sight gains of 3.0 dBic(L1) and 5.1 dBic(L2), and axial ratios of 3.3 dB(L1) and 0.3 dB(L2) by measurement. The active element patterns of the fabricated array with 7 elements show bore-sight gains of -0.4 dBic (L1) and -2.4 dBic(L2), respectively. It proves that the proposed antenna structure is suitable for use in GPS array applications.

• The KIPS Transactions:PartB
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• v.13B no.5 s.108
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• pp.507-514
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• 2006

Various application systems are developed using RFID as a part of ubiquitous computing, and it is expected that RFID chip will become wide-spread for the distribution industry especially. Efficient and efact intelligent-type of warehouse management system is essential for small-to-medium-sized enterprises in the situation having a trouble in the viewpoint of expense and manpower. In this paper, we implement small-scale warehouse management system using log-based context awareness technology. This system is implemented to be controlled on web, configuring clients to control RFID readers and building up DBMS system in a server. Especially, it grasps user's intention of storing or delivering based on toE data for the history of user's access to the system and it reports user's irregular pattern of warehouse use and serves predictive information of the control of goods in stock. As a result, the proposed system can contribute to enhance efficiency and correctness of small-scale warehouse management.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1346-1353
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• 1996

In this paper, we propose a modeling method for the flip-flops and test generation algorithms to detect the faults in the sequential circuits using VHDL in the high-level design environment. RS, JK, D and T flip-flops are modeled using data flow types. The sequence of micro-operation which is the basic structure of a chip-level leads to a control point where varnishing occurs to one of two micro- operation sequence. In order to model the fault of one micro-operation(FMOP) that perturb another micro-operation effectively, the concept of goal trees and some heuristic rules are used. Given a faulty FMOP or fault of control point (FCON), a test pattern is generated by fault sensitization, path sensitization and determination of the imput combinations that will justify the path sensitization. The fault models are restricted to the data flow model in the ARCHITECTURE statement of VHDL. The proposed algorithm is implemented in the C language and its efficiency is confirmed by some examples.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.46-56
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• 1991

In this paper, 16word X 8bit Content Addressable and Reentrant Memory(CARM) is described. This device has 4 operation modes(read, write, match, reentrant). The read and write operation of CARM is like that of static RAM, CARM has the reentrant mode operation where the on chip garbage collection is accomplished conditionally. Thus function can be used for high speed matching unit of dynamic data flow computer. And CARM also can encode matching address sequentially according to therir priority. CARM consists of 8 blocks(CAM cell, Sequential Address Encoder(S.A.E). Reentrant operation. Read/Write control circuit, Data/Mask Register, Sense Amplifier, Encoder. Decoder). Designed DARM can be used in data flow computer, pattern, inspection, table look-up, image processing. The simulation is performed using the QUICKSIM logic simulator and Pspice circuit simulator. Having hierarchical structure, the layout was done using the 3{\;}\mu\textrm{m} n well CMOS technology of the ETRI design rule.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.26-34
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• 1999

A new silicon-based IC interconnect transmission line parameter extraction methodology is presented and experimentally examined. Unlike the PCB or MCM interconnects, a dominant energy propagation mode in the silicon-based IC interconnects is not quasi-TEM but slow wave mode(SWM). The transmission line parameters are extracted taking the silicon substrate effect (i.e., slow wave mode) into account. The capacitances are calculated considering silicon substrate surface as a ground. Whereas the inductances are calculated by using an effective dielectric constant. In order to verify the proposed method, test patterns were designed. Experimental data have agreement within 10%. Further, crosstalk noise simulation shows excellent agreements with the measurements which are performed with high-speed time domain measurement ( i.e., TDR/TDT measurements) for test pattern, while RC model or RLC model without silicon substrate effect show about 20~25% underestimation error.

• Molecular & Cellular Toxicology
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• v.2 no.2
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• pp.120-125
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• 2006

Phenytoin is an anti-epileptic. It works by slowing down impulses in the brain that cause seizures. The recent microarray technology enables us to understand possible mechanisms of genes related to compounds which have toxicity in biological system. We have studied that the effect of a compound related to hepatotoxin in vitro system using a rat whole genome microarray. In this study, we have used a rat liver epithelial cell line WB-F344 and phenytoin as a hepatotoxin. WB-F344 was treated with phenytoin for 1 to 24 hours. Total RNA was isolated at times 1, 6 and 24h following treatment of phenytoin, and hybridized to the microarray containing about 22,000 rat genes. After analysis with clustering methods, we have identified a total of 1,455 differentially expressed genes during the time course. Interestingly, about 1,049 genes exhibited differential expression pattern in response to phenytoin in early time. Therefore, the identification of genes associated with phenytoin in early response may give important insights into various toxicogenomic studies in vitro system.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.61-64
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• 2000

We fabricated and characterized Low Noise Amplifier (LNA) using MCM-C (Multi-Chip-Module-Cofired) technology for 2.14 GHz IMT-2000 mobile terminal application. First, We designed LNA circuits and simulated it's high frequency characteristics using circuits simulator. For the simulation, we adopted high frequency libraries of all the devices used in LNA samples. By the simulation, Gain was 17 dB and Noise Figure was 1.4 dB. We used multilayer process of LTCC (Low Temperature Co-fired Ceramics) substrate and conductor, resistor pattern for the MCM-C LNA fabrication. We made 2 buried inductors, 2 buried capacitors and 3 buried resistors. The number of the total layers was 6. On the top layer, we patterned microstrip line and pads for the SMT device. We measured the high frequency characteristics, and the results were 14.7 dB Gain and 1.5 dB Noise Figure.