• Journal of the Korea Society of Computer and Information
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• v.4 no.2
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• pp.46-60
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• 1999

Recently, CTI (Computer Telephony Integration) technology has been widely applied to various area such as video conference, file transfer, voice mail, automatic message transfer and automatic redial, integrated messaging and network fax. In this paper, an administrative affairs supporting system using call control mode of CTI is designed. To improve inefficient processing of job due to heavy calling from entrance candidates during entrance examination of a college, the system is developed. The database of the system is desigend using object modeling technique. Also, the automatic calling and response system using CTI call control mode is implemented. Especially, to interface with voice of candidates who ask whether they pass or fail the entrance examination of the college, TTS(Text To Speech) module is developed.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.3
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• pp.79-84
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• 2011

In this paper, we analyzed performance of vehicle detection for ITS (Intelligent Transport System) applications. We simulated the vehicle detection at Hi-Pass System is based on DSRC (Dedicated Short Range Communication). DSRC is a wireless network using ITS, including GPS (Global Positioning System) satellites in conjunction with the national transportation system. The system performance is evaluated in terms of bit error probability. In the simulation, the vehicle speed is set at 60 km/h and carrier frequency is 5.8 GHz. Wireless channel is modeled as the Rician fading channel. In the transmitter, the ASK (amplitude shift keying) modulation scheme is applied. From simulation results, we confirmed that performance of applied Alamouti scheme is better than other systems.

• Transactions of Materials Processing
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• v.27 no.3
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• pp.154-159
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• 2018

In the rectangular bar multi-stage drawing process, the cross-section dimensional accuracy of the rectangular bar varies depending on the aspect ratio and process conditions. It is very important to predict the dimensional error of the cross-section occurring in the multi-stage drawing process according to the aspect ratio of the rectangular bar and the half die angle of each pass. In this study, a process map for improving the dimensional accuracy according to the aspect ratio was derived in the drawing process of a rectangular bar. FE-simulation of the multi-stage shape drawing process was carried out with four types of rectangular bar. The results of the FE-simulation were trained to the nonlinear relationship between the shape parameters using an Artificial Neural Network (ANN), and the process maps were derived from them. The optimum half die angles were determined from the process maps on the dimensional accuracy. The validity of the suggested process map for aspect ratios 1.25~2:1 were verified through FE-simulation and experimentation.

• Structural Engineering and Mechanics
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• v.75 no.2
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• pp.271-282
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• 2020

The preservation of historic masonry-arch railway bridges is of paramount importance due to their economic benefits. These bridges which belong to past centuries may nowadays be expected to carry loads higher than those for which they were designed. Such an increase in loads may be because of increase in transportation speed or in the capacity of freight-wagons. Anyway, adequate increase in their load-carrying-capacity through structural-strengthening is required. Moreover, the increasing costs of material/construction urge engineers to optimize their designs to obtain the minimum-cost one. This paper proposes a novel numerical optimization method to minimize the costs associated with strengthening of masonry-arch railway bridges. To do so, the stress/displacement responses of Sahand-Goltappeh bridge are assessed under ordinary train pass as a case study. For this aim, 3D-Finite-Element-Model is created and calibrated using experimental test results. Then, it is strengthened such that following goals are achieved simultaneously: (1) the load-carrying-capacity of the bridge is increased; (2) the structural response of the bridge is reduced to a certain limit; and, (3) the costs needed for such strengthening are minimized as far as possible. The results of the case study demonstrate the applicability/superiority of the proposed approach. Some economic measures are also recommended to further reduce the total strengthening cost.

• Journal of Korea Multimedia Society
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• v.17 no.11
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• pp.1307-1312
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• 2014

Online games are virtual space where it connects individual users through network connection to offer enjoyment of play games and game developer who service online games have to develop new contents and provide them to users to extend life of their service. Typically, in order to update new contents, all service companies have maintenance schedule to stop the game service for a while to update both server and client applications. Usually this process takes quite amount of time and users do not have any other choice but disconnected from server and wait until it is over. The purpose of this thesis is to describe the advantages of new design system which will allows users to continue to play the game even during the update. The main focus of this design is to make users feel more convenience in online gaming experience by move client from previous server to new server while users are still playing. If they can to connect current client with new server without any certificate validation process while users information from the client can automatically pass through to the new server, users may not need to experience maintenance for new contents update.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.299-302
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• 2008

In this paper, A compact ultra-wideband(UWB) bandpass filter(BPF) with WLAN notched filter has been proposed. H-shaped slot is studied and adopted to tighten the coupling of inter-digital capacitor in order to improve the BPF's performance. Three pairs of tapered defected ground structures(DGS) are formed to assign their transmission zeros towards the out of band signal, thereby suppressing the spurious passband. Also Meander line slot is developed to reject the undesired wireless local-area network(WLAN) radio signals. That's combining these three structures we obtain a small sized UWB BPF.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.184-191
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• 1993

Continuous-time integrated filters, implemented in MOS VLSI technology, have been receiving considerable attention. In this paper, a continuous-time fifth order elliptic low-pass MOSFET-C filter has been designed with a cutoff frequency 3,400Hz. First an active RC filter is designed using cascade method which each block can be tunable. And then the resistors of an active RC network are replaced by a linear resistor using NMOS depletion transistors operated in the triode region. This continuous-time MOSFET filter have simpler structure than switched-capacitor filter, so reduce the chip area. The designed MOSFET-C filter characteristics are simulated by PSPICE program.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.9
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• pp.4576-4598
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• 2018

In big data age, flexible and affordable cloud storage service greatly enhances productivity for enterprises and individuals, but spontaneously has their outsourced data susceptible to integrity breaches. Provable Data Possession (PDP) as a critical technology, could enable data owners to efficiently verify cloud data integrity, without downloading entire copy. To address challenging integrity problem on multiple clouds for multiple owners, an identity-based batch PDP scheme was presented in ProvSec 2016, which attempted to eliminate public key certificate management issue and reduce computation overheads in a secure and batch method. In this paper, we firstly demonstrate this scheme is insecure so that any clouds who have outsourced data deleted or modified, could efficiently pass integrity verification, simply by utilizing two arbitrary block-tag pairs of one data owner. Specifically, malicious clouds are able to fabricate integrity proofs by 1) universally forging valid tags and 2) recovering data owners' private keys. Secondly, to enhance the security, we propose an improved scheme to withstand these attacks, and prove its security with CDH assumption under random oracle model. Finally, based on simulations and overheads analysis, our batch scheme demonstrates better efficiency compared to an identity based multi-cloud PDP with single owner effort.