• Title/Summary/Keyword: Parasitics

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An MMIC VCO Design and Fabrication for PCS Applications

  • Kim, Young-Gi;Park, Jin-Ho
    • Journal of Electrical Engineering and information Science
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    • v.2 no.6
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    • pp.202-207
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    • 1997
  • Design and fabrication issues for an L-band GaAs Monolithic Microwave Integrated Circuit(MMIC) Voltage Controlled Oscillator(VCO) as a component of Personal Communications Systems(PCS) Radio Frequency(RF) transceiver are discussed. An ion-implanted GaAs MESFET tailored toward low current and low noise with 0.5mm gate length and 300mm gate width has been used as an active device, while an FET with the drain shorted to the source has been used as the voltage variable capacitor. The principal design was based on a self-biased FET with capacitive feedback. A tuning range of 140MHz and 58MHz has been obtained by 3V change for a 600mm and a 300mm devices, respectively. The oscillator output power was 6.5dBm wth 14mA DC current supply at 3.6V. The phase noise without any buffer or PLL was 93dB/1Hz at 100KHz offset. Harmonic balance analysis was used for the non-linear simulation after a linear simulation. All layout induced parasitics were incorporated into the simulation with EEFET2 non-linear FET model. The fabricated circuits were measured using a coplanar-type probe for bare chips and test jigs with ceramic packages.

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Drain Current Response Delay High Frequency Model of SOI MOSFET with Inductive Parasitic Elements (유도성 기생성분에 의한 드레인전류 응답지연을 포함한 SOI MOSFET 고주파모델)

  • Kim, Gue-Chol
    • The Journal of the Korea institute of electronic communication sciences
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    • v.13 no.5
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    • pp.959-964
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    • 2018
  • In this paper, it was firstly confirmed that the drain current of the depleted SOI MOSFET operated in the high frequency response delay occurs by the inductive parasitic. Depleted SOI MOSFET cannot be applied as a conventional high-frequency MOSFET model because the response delay of the drain current is generated in accordance with the drain voltage fluctuation. This response delay may be described as a non-quasi-static effect, and the SOI MOSFET generated the response delay by the inductive parasitics compared to typical MOSFET. It is confirmed that depleted SOI MOSFET's RF characteristics can be well reproduced with the proposed method including the drain current response delay.

Wideband Characterization of Double Bondwires Ribbon for Millimeter-Wave Packaging (밀리미터파 대역 패키징을 위한 이중 본드와이어와 리본의 광대역 특성)

  • Kim, Jin-Yang;Chang, Dong-Pil;Yom, In-Bok;Lee, Hai-Young
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.7
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    • pp.7-13
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    • 2001
  • The wirebonding is a common interconnection technique for modern microwave devices because of rather simple and reliable processes involved. At millimeter-wave frequencies, however, the bondwire parasitics are significant and consequently limit the external performance of packaged devices. In this paper, we represent wideband characterization of multiple bondwires and ribbon in a frequency range from 20 to 35 GHz. From these results, the double bondwire shows very small insertion loss less than 0.55 dB up to 35 GHz and its performance is comparable to that of the ribbon in the millimeter-wave frequencies. Therefore, the wirebonding is very suitable for millimeter wave packaging in terms of performance and manufacturing cost.

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A Study on AC Modeling of the ESD Protection Devices (정전기 보호용 소자의 AC 모델링에 관한 연구)

  • Choi, Jin-Young
    • Journal of IKEEE
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    • v.8 no.1 s.14
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    • pp.136-144
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    • 2004
  • From the AC analysis results utilizing a two dimensional device simulator, the ac equivalent-circuit modeling of the ESD protection devices is executed. It is explained that the ac equivalent circuit of the NMOS protection transistor is modeled by a rather complicated form and that, depending on the frequency range, the error can be large if it is modeled by a simple RC serial circuit. It is also shown that the ac equivalent circuit of the thyristor-type pnpn protection device can be modeled by a simple RC serial circuit. Based on the circuit simulations utilizing the extracted equivalent circuits, the effects of the parasitics in the protection device on the characteristics of LNA are examined when the LNA, which is one of the important RF circuits, is equipped with the protection device. It is explained that a large error can result in estimating the circuit characteristics if the NMOS protection transistor is modeled by a simple capacitor. It is also confirmed that the degradation of the LNA characteristics by incorporating the ESD protection device can be reduced a lot by adopting the suggested pnpn device.

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A Study on the Extraction of Parasitic Inductance for Multiple-level Interconnect Structures (다층배선 인터커넥트 구조의 기생 인덕턴스 추출 연구)

  • Yoon, Suk-In;Won, Tae-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.7
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    • pp.16-25
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    • 2002
  • This paper presents a methodology and application for extracting parasitic inductances in a multi-level interconnect semiconductor structure by a numerical technique. In order to calculate the parasitic inductances, the distrubution of electric potential and current density in the metal lines are calculated by finite element method (FEM). Thereafter, the magneto-static energy caused by the current density in metal lines was calculated. The result of simulation is compared with the result of Grover equation about analytic simple structures, and 4 bit ROM array with a dimension of $13{\times}10.25{\times}8.25{\mu}m^3$ was simulated to extract the parasitic inductnaces. In this calculation, 6,358 nodes with 31,941 tetrahedra were used in ULTRA 10 workstation. The total CPU time for the simulation was about 150 seconds, while the memory size of 20 MB was required.

A Study on the Extraction of Cell Capacitance and Parasitic Capacitance for DRAM Cell Structures (DRAM 셀 구조의 셀 캐패시턴스 및 기생 캐패시턴스 추출 연구)

  • Yoon, Suk-In;Kwon, Oh-Seob;Won, Tae-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.7
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    • pp.7-16
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    • 2000
  • This paper reports a methodology and its application for extracting cell capacitances and parasitic capacitances in a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitances, we employed finite element method (FEM), The three-dimensional DRAM cell structure is generated by solid modeling based on two-dimensional mask layout and transfer data. To obtain transfer data for generating three-dimensional simulation structure, topography simulation is performed. In this calculation, an exemplary structure comprising 4 cell capacitors with a dimension of $2.25{\times}1.75{\times}3.45{\mu}m^3$, 70,078 nodes with 395,064 tetrahedra were used in ULTRA SPARC 10 workstation. The total CPU time for the simulation was about 25 minutes, while the memory size of 201MB was required. The calculated cell capacitance is 24.34fF per cell, and the influential parasitic capacitances in a stacked DRAM cell are investigated.

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Design and Fabrication of Diplexer for Dual-band GSM/DCS Application using High-Q Multilayer Inductors (고품질 적층형 인덕터를 이용한 이중 대역 GSM/DCS 대역 분리용 다이플렉서의 설계 및 제작)

  • 심성훈;강종윤;최지원;윤영중;윤석진;김현재
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.15 no.2
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    • pp.165-171
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    • 2004
  • In this paper, the modeling and design of high-Q multilayer passives have been investigated, and multilayer diplexer for GSM/DCS applications has been designed and fabricated using the passives. Modeling of a multilayer inductor was performed by the subsystems of distributed components, and using the modeling the optimal structures of the high-Q multilayer inductor could be designed by analyzing parasitics and couplings which affect their frequency characteristics. Multilayer diplexers for GSM/DCS applications have been designed and fabricated using LTCC technology. LPF for GSM band had the passband insertion loss of less than 0.55 dB, the return loss of more than 12 dB, and the isolation level of more than 26 dB. HPF for DCS band had the passband insertion loss of less than 0.82 dB, the return loss of more than 11 dB, and the isolation level of more than 38 dB.

A High Power SP3T MMIC Switch (고출력 SP3T MMIC 스위치)

  • 정명득;전계익;박동철
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.11 no.5
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    • pp.782-787
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    • 2000
  • The monolithic single-pole three-throw(SP3T) GaAs PIN diode switch circuit for the broadband and high power application was designed, fabricated and characterized. To improve the power handling capability, buffer layers of the diode employ both low temperature buffer and superlattice buffer. The diode show the breakdown voltage of 65V and turn-on voltage of 1.3V. The monolithic integrated switch employed microstrip lines and backside via holes for low-inductance signal grounding. The vertical epitaxial PIN structure demonstrated better microwave performance than planar type structures due to lower parasitics and higher quality intrinsic region. As the large signal characteristics of the fabricated SP3T MMIC switch, the insertion loss was measured less than 0.6dB and the isolation better than 50dB when the input power was increased from 8dBM to 32dBm at 14.5GHz.

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Design of Power Detection Block for Wireless Communication Transmitter Systems (무선통신 송신시스템용 전력검출부 설계)

  • Hwang, Mun-Su;Koo, Jae-Jin;Ahn, Dal;Lim, Jong-Sik
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.8 no.5
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    • pp.1000-1006
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    • 2007
  • This paper presents a power detector circuit which monitors the transmitting power for the application in CDMA cell phones. The proposed power detector are composed of coupler for coupling output power and detector fur monitoring output power. The designed coupler has low loss characteristic because it adopts the stripline structure which consists of two ground planes at both sides of signal plane. The design frequency is 824-849MHz which is the Tx band fur CDMA mobile terminal, and the coupling factor of the stripline coupler is -20dB. A schottky barrier diode is adopted for detector design because of its high speed operation with minimized loss. The required impedance matching is performed to improve the linearity and sensitivity of output voltage at relatively low detector input level where the nonlinear characteristic of diode exists. The package parasitics as well as intrinsic diode model are considered for simulation of the detector. The predicted performances agree well with the measured results.

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Effects of crude Saponin on growth and Aflatoxin production by Aspergillus parasiticus (Saponin이 Aspergillus parasiticus의 발육과 Aflatoxin생합성에 미치는 효과)

  • 박재림;임광식;이종근
    • Korean Journal of Microbiology
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    • v.23 no.4
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    • pp.259-264
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    • 1985
  • The research was carried out for the purpose of finding effects of gerbal saponins on aflatoxin synthesis by Aspergillus parasitics NRRL 2999. A. parasiticus with $10^6$ conidia were grown at $30^{\circ}C$ for 9 days on the enriched medium that is optimum for the frowth and aflatoxins production by the mold. The inhibitory effect on the growth and aflatoxins produced by the mold occurred in the presence of 0.36% of crude red-ginseng saponin showing both the growth and aflatoxins production come to 62.3% (growth), 38.7% (aflatoxin $B_1$) and 22.9% (aflatoxin $G_1$) of the control. Thd next effective saponin to inhibit the growth and aflatoxins production was from burdock seeds. However, saponin extracted from honeysuckle flowers had no inhibitory effect. The mold caused no changes in the pH of the medium when it contained red-ginseng saponin. Red-ginseng saponin was more effective than the white-ginseng in inhibiting both the growth and aflatoxin production.

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