• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.4
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• pp.538-542
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• 2018

In order to generate a clock source with low cost and high performance in system on chip(SoC), a relaxation oscillator with stable output characteristics according to PVT(process, voltage and temperature) fluctuation require a low area and a low power. In this paper, we propose a solution to reduce the current loss caused by parasitic components in the conventional relaxation oscillator. Since the slew rate of the bias current and the capacitor are adjusted to be the same through the proposed solution, a relaxation oscillator with low area characteristics is designed for the same clock source frequency implementation. The proposed circuit is designed using the TSMC CMOS 0.18um process. The Simulation results show that the relaxation oscillator using the proposed solution can prevent the current loss of about $279{\mu}A$ and reduce the total chip area by 20.8% compared with the conventional oscillator in the clock source frequency of 96 MHz.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.485-490
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• 2010

We propose the equivalent circuit model including all parasitic components in input gate of sense amplifier of DDI DRAM with butting contact structure. We analysed the effect of parasitic schottky diode by using the proposed model in the operation of sense amplifier. The cause of single side fail and the temperature dependence of fail rate in DDI DRAM are due to creation of the parasitic schottky diode in input gate of sense amplifier. The parasitic schottky diode cause the voltage drop in input gate, and result in decreasing noise margin of sense amplifier. therefore single side fail rate increase.

• ETRI Journal
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• v.41 no.6
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• pp.715-730
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• 2019

We propose a switched beam-forming antenna that satisfies not only ultra-wideband characteristics but also beam-forming in the WLAN frequency band using an ultra-wideband antenna and passive parasitic elements applying a broadband optimal reactance load algorithm. We design a power and phase estimation function and an error correction function by re-analyzing and normalizing all the components of the parasitic array using control system engineering. The proposed antenna is compared with an antenna with a pin diode and reactance load value, respectively. The pin diode is located between the passive parasitic elements and ground plane. An antenna beam can be formed in eight directions according to the pin diode ON (reflector)/OFF (director) state. The antenna with a reactance load value achieves a better VSWR and gain than the antenna with a pin diode. We confirm that a beam is formed in eight directions owing to the RF switch operation, and the measured peak gain is 7 dBi at 2.45 GHz and 10 dBi at 5.8 GHz.

• Journal of Sensor Science and Technology
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• v.19 no.3
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• pp.191-196
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• 2010

In this paper, modeling of the non-ideal frequency response, especially "notch-and-spike" magnitude phenomenon and phase lag distortion, are discussed. To characterize the non-ideal frequency response, a new electro-mechanical simulation model based on SPICE is proposed using the driving loop of the capacitive vibratory gyroscope. The parasitic components of the driving loop are found to be the major factors of non-ideal frequency response, and it is verified with the measurement results.

• ETRI Journal
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• v.31 no.6
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• pp.778-783
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• 2009

To fabricate uniform and reliable thin gold stripes that provide low-loss optical waveguides, we developed a novel liftoff process placing an additional $SiN_x$ layer under conventional photoresists. By patterning a photoresist and over-etching the $SiN_x$, the photoresist patterns become free-standing structures on a lower-cladding. This leads to uniform metal stripes with good reproducibility and effectively removes parasitic structures on the edge of the metal stripe in the image reversal photolithography process. By applying the newly developed process to polymer-based gold stripe waveguide fabrication, we improved the propagation losses about two times compared with that incurred by the conventional image-reversal process.

• ETRI Journal
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• v.15 no.3
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• pp.61-69
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• 1994

A new analytical model for the base current of Si/SiGe/Si heterojunction bipolar transistors(HBTs) has been developed. This model includes the hole injection current from the base to the emitter, and the recombination components in the space charge region(SCR) and the neutral base. Distinctly different from other models, this model includes the following effects on each base current component by using the boundary condition of the excess minority carrier concentration at SCR boundaries: the first is the effect of the parasitic potential barrier which is formed at the Si/SiGe collector-base heterojunction due to the dopant outdiffusion from the SiGe base to the adjacent Si collector, and the second is the Ge composition grading effect. The effectiveness of this model is confirmed by comparing the calculated result with the measured plot of the base current vs. the collector-base bias voltage for the ungraded HBT. The decreasing base current with the increasing the collector-base reverse bias voltage is successfully explained by this model without assuming the short-lifetime region close to the SiGe/Si collector-base junction, where a complete absence of dislocations is confirmed by transmission electron microscopy (TEM)[1].The recombination component in the neutral base region is shown to dominate other components even for HBTs with a thin base, due to the increased carrier storage in the vicinity of the parasitic potential barrier at collector-base heterojunction.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.4
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• pp.384-394
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• 1999

This paper deals with a fixed frequency full-bridge inverter type DC-DC high-power converter with high frequency high voltage(HFHV) transformer-coupled stage, which operates under quasi-resonant ZVS transition priciple in spite of a wide PWM-based voltage regulation processing and largely-changed load conditions. This multi-resonant(MR) converter topology is composed of a series capacitor-connected parallel resonant tank which makes the most of parasitic circuit reactive components of HFHV transformer and two additional quasi-resonant pole circuits incorporated into the bridge legs. The soft-switching operation and practical efficacy of this new converter circuit using the latest IGBTs are actually ascertained through 50kV trially-produced converter system operating using 20kHz/30kHz high voltage(HV) transformers which is applied for driving the diagnostic HV X-ray tube load in medical equipments. It is proved from a practical point of view that the switching losses of IGBTs and their electrical dynamic stresses relating to EMI noise can be considerably reduced under a high frequency(HF) switching-based phase-shift PWM control process for a load setting requirements.

• Journal of Power Electronics
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• v.6 no.1
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• pp.73-82
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• 2006

Plasma display panels (PDPs) have a serious thermal problem, because the luminance efficiency of a conventional PDP is about 1.5 1m/W and it is less than $3\~5\;lm/W$ of a cathode ray tube (CRT). Thus there is a need for improving the luminance efficiency of the PDP. There are several approaches to improve the luminance efficiency of the PDP and we adopted a driving PDP at high frequency range from 400kHz up to over 700kHz. Since a PDP is regarded as an equivalent inherent capacitance, many types of sustaining drivers have been proposed and widely used to recover the energy stored in the PDP. However, these circuits have some drawbacks for driving PDPs at high frequency ranges. In this paper, we investigate the effect of the parasitic components on the PDP itself and on the driver when the reactive energy of the panel is recovered. Various drivers are classified and evaluated based on their suitability for high frequency drivers. Finally, a current-fed driver with a DC input voltage bias is proposed. This driver overcomes the effect of parasitic components in the panel and driver. It fully achieves a ZVS of all full-bridge switches and reduces the transition time of the panel polarity. It is tested to validate the high frequency sustaining driver and the experimental results are presented.

• Journal of IKEEE
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• v.21 no.3
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• pp.260-263
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• 2017

Based on several CPU cores, an SoC including ADCs, DC-DC converter and 2M-byte SRAM is proposed in this paper. The CPU core consists of a 12-bit MENSA, a 32-bit Symmetric multi-core processor, as well as 16-bit CDSP. To eliminate the external SDRAM memory, internal 2M-byte SRAM is implemented. Because the SRAM normally occupies huge area, the parasitic components reduce the speed of SoC. In this work, the SRAM blocks are divided into small pieces to reduce the parasitic components. The proposed SoC is developed in a standard 55nm CMOS process and the speed of SoC is 200MHz.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.3
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• pp.176-182
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• 2021

This research proposes a high-frequency circuit that can accurately predict the differential mode noise of single-phase inverters at the circuit design stage. Proposed single-phase inverter high frequency circuit in the work is a form in which harmonic impedance components are added to the basic single-phase inverter circuit configuration. For accurate noise prediction, parasitic components present in each part of the differential noise path were extracted. Impedance was extracted using a network analyzer and Q3D in the measurement range of 150 kHz to 30 MHz. A high-frequency circuit model was completed by applying the measured values. Simulations and experiments were conducted to confirm the validity of the high-frequency circuit. As a result, we were able to predict the resonance point of the differential mode voltage extracted as an experimental value with a high-frequency circuit model within an approximately 10% error. Through this outcome, we could verify that differential mode noise can be accurately predicted using the proposed model of the high-frequency circuit without a separate test bench for noise measurement.