• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.1
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.7 no.5
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• pp.395-407
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• 1996

In this paper, we describe the crossover of the parasitic capacitance at the interconnections for the system miniature, analyse ground capacitance and mutual capacitance due to actually coupled line in the ICs or MCMs. From the results of deviding interconnection line with infinite parts, using Green's function with image charge method and moments, we could obtain 70% decrease of system runtime parasitic inductance because of simplicity of transforming formular.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.653-657
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• 2015

A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.

• Journal of Power Electronics
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• v.18 no.3
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• pp.892-901
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• 2018

SiC MOSFETs have been used to improve system efficiency in high frequency converters due to their extremely high switching speed. However, this can result in undesirable parasitic oscillations in practical systems. In this paper, models of the key components are introduced first. Then, theoretical formulas are derived to calculate the switching oscillation frequencies after full turn-on and turn-off in clamped inductive circuits. Analysis indicates that the turn-on oscillation frequency depends on the power loop parasitic inductance and parasitic capacitances of the freewheeling diode and load inductor. On the other hand, the turn-off oscillation frequency is found to be determined by the output parasitic capacitance of the SiC MOSFET and power loop parasitic inductance. Moreover, the shifting regularity of the turn-off maximum peak voltage with a varying switching speed is investigated on the basis of time domain simulation. The distortion of the turn-on current is theoretically analyzed. Finally, experimental results verifying the above calculations and analyses are presented.

• Journal of electromagnetic engineering and science
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• v.7 no.3
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• pp.116-121
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• 2007

Novel design of a wideband monopole antenna for DVB-H service is presented. The proposed antenna is designed based on a monopole antenna. It consists of folded monopole and parallel parasitic element. The folded segment of the folded monopole makes the antenna shorter. The length of the parasitic element obtains additional resonance frequencies. The gap distance between the folded monopole and the parasitic element is a key parameter to control impedance matching for wideband operation. The antenna has wide band performance, good impedance and radiation characteristics from 470 MHz to 870 MHz. The measured return loss for operating frequencies over DVB-H band is better than 10 dB. Good radiation patterns are also obtained. The measured results are compared with calculated results using Ansoft HFSS(High Frequency Structure Simulator).

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.671-674
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• 2005

The series parasitic resistances ($R_s$, $R_g$, $R_d$, $R_{sub}$) of BSIM3v3 RF MOSFET macro model were directly extracted from measured S-parameters in the GHz region by using simple 2-port parameter equations. Also, overlap capacitance and junction capacitance parameters were extracted by tuning $S_{11}$, $S_{12}$, and $S_{22}$ respectively while DC-parameters and all parasitic resistances are fixed at previously extracted values. These data are verified to be accurate by observing good correspondence between modeled and measured S-parameters up to 10GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.12
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• pp.1059-1068
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• 2016

This paper proposes slow wave structure(SWS) utilized to increase antenna gain of printed dipole antenna(PDA) and to suppress sidelobe level simultaneously, and makes sure of electrical characteristics of the antenna according to parameter variations of components of the slow wave structure. The printed slow wave structure which is composed of a dielectric substrate and a metal rods array is located on excited direction of the PDA, affecting the radiation pattern and its intensity. Parasitic elements of the metal rods are arrayed in narrow consistent gap and have a tendency to gradually decrease in length. In this paper, array interval, element length, and taper angle are selected as the parameter of the parasitic element that effects radiation characteristics. Magnitude and phase distribution of the electrical field are observed and analyzed for each parameter variations. On the basis of these results, while the radiation pattern is analyzed, array methods of parasitic elements of the SWS for high gain characteristics are provided. The proposed antenna is designed to be operated at the Wifi band(5.15~5.85 GHz), and parameters of the parasitic element are optimized to maximize antenna gain and suppress sidelobe. Simulated and measured results of the fabricated antenna show that it has wide bandwidth, high efficiency, high gain, and low sidelobe level.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.155-161
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• 2007

This paper presents the design simulation, implementation, and measurement of a miniaturized PCS / Satellite DMB dual-band stacked mompole antenna with a parasitic patch for mobile communication terminals. A stacked helix is realized by using a via hole with height of 0.4 mm and a diameter of 0.35 mm to connect upper- and lower-layer helix sections for a reduction of the dimensions of the antenna. In addition the stacked helix chip antenna is interleaved with a parasitic patch to achieve two different radiation modes. The ratio of the first frequency and the second frequency vary with the geometrical parameter of the parasitic patch. The fabricated antenna uses FR-4 substrate with a relative permittivity of 4.2. Its dimensions are $15.5{\times}7.6{\times}0.4 mm^3$. The measured impedance bandwidths (VSWR<2) are 240 and 250 MHz at the operating frequencies, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.964-973
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• 2017

In this paper, we analyze the effects of parasitic components of common-mode choke on the common mode and differential mode in a wide band, and we propose a simple method for high-frequency modeling. Common mode and differential mode 2-port networks were configured and the S-parameters in each mode were measured using a network analyzer. Equivalent circuit elements were extracted from the measured results to model a high-frequency equivalent circuit, and the validity was verified by comparing the measured S-parameters with the simulation results.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.55-59
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• 2013

A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-$0.1{\mu}m$. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of $0.065{\mu}m$.