• Communications for Statistical Applications and Methods
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• v.31 no.3
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• pp.263-277
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• 2024

This paper proposes new parameterizations of the tilted beta binomial distribution, obtained from the combination of the binomial distribution and the tilted beta distribution, where the beta component of the mixture is parameterized as a function of their mean and variance. These new parameterized distributions include as particular cases the beta rectangular binomial and the beta binomial distributions. After that, we propose new linear regression models to deal with overdispersed binomial datasets. These new models are defined from the proposed new parameterization of the tilted beta binomial distribution, and assume regression structures for the mean and variance parameters. These new linear regression models are fitted by applying Bayesian methods and using the OpenBUGS software. The proposed regression models are fitted to a school absenteeism dataset and to the seeds germination rate according to the type seed and root.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.93-96
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decode. is parameterized for the code rates 1/2, 1/3 and constraint lengths 7, 9, thus it has four operation modes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.1-11
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• 1999

In this paper, we proposed a design method of parameterized viterbi decoder, which automatically synthsizes the diverse viterbi deciders used in the digital mobile communication systems. It is designed to synthesize a viterbi decoder specified by user-provided parameters. Those parameters are constraint length, code rate generator polynomials of teh convolutional encoder, data rate and bits/frame of the data transmission, and soft decision bits of viterbi decoder. For the design of the parameterized viterbi decoder, we designed a user interface module C-language, and a viterbi decoder module in a hierarchical atructure using VHDL language and its generic statement. For the verification of the parameterized viterbi decoder, we compared our synthesized viterbi decoder with the conventional viterbi decoder which is designed for the IS-95 CDMA system. The proposed design method of the viterbi decoder will be a new method to obtain a required viterbi decoder in a very short time only by supplying the design parameters.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.3
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• pp.32-41
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• 2008

In this paper, we describe the synthesis of robust and non-fragile $H^{\infty}$ state feedback controllers for linear systems with affine parameter uncertain tracking servo system of blu-ray disc drive, as well as static state feedback controller with polytopic uncertainty Similarity any other control system, the objective of the track-following system design for optical disc drives is to construct the system with better performance and robustness against modeling uncertainties and various disturbances. Also, the obtained condition can be rewritten as parameterized linear matrix inequalities(PLMIs), that is, LMIs whose coefficients are functions of a parameter confined to a compact set. We show that the resulting controller guarantees the asymptotic stability and disturbance attenuation of the closed loop system in spite of controller gain variations within a resulted polytopic region.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.8
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• pp.1911-1932
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• 2013

Orthogonal frequency-division multiplexing (OFDM) has become a popular modulation scheme for wireless protocols because of its spectral efficiency and robustness against multipath interference. Although the components of various OFDM protocols are functionally similar, they remain distinct because of the characteristics of the environment. Recently, graphics processing units (GPUs) have been used to accelerate the signal processing of the physical layer (PHY) because of their great computational power, high development efficiency, and flexibility. In this paper, we describe the implementation of parameterized baseband modules using GPUs for two different OFDM protocols, namely, 802.11a and 802.16. First, we introduce various modules in the modulator/demodulator parts of the transmitter and receiver and analyze the computational complexity of each module. We then describe the integration of the GPU-based baseband modules of the two protocols using the parameterized method. GPU-based implementations are addressed to explain how to accelerate the baseband processing to archive real-time throughput. Finally, the performance results of each signal processing module are evaluated and analyzed. The experiments show that the GPU-based 802.11a and 802.16 PHY meet the real-time requirement and demonstrate good bit error ratio (BER) performance. The performance comparison indicates that our GPU-based implemented modules have better flexibility and throughput to the current ones.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.183-190
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• 2002

This paper describes the synthesis of robust and non-fragile H$\infty$ state feedback controllers for linear varying systems with affine parameter uncertainties, and static state feedback controller with structured uncertainty. The sufficient condition of controller existence, the design method of robust and non-fragile H$\infty$ static state feedback controller, and the set of controllers which satisfies non-fragility are presented. The obtained condition can be rewritten as parameterized Linear Matrix Inequalities(PLMls), that is, LMIs whose coefficients are functions of a parameter confined to a compact set. However, in contrast to LMIs, PLMIs feasibility problems involve infinitely many LMIs hence are inherently difficult to solve numerically. Therefore PLMls are transformed into standard LMI problems using relaxation techniques relying on separated convexity concepts. We show that the resulting controller guarantees the asymptotic stability and disturbance attenuation of the closed loop system in spite of controller gain variations within a degree.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.12
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• pp.1926-1933
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• 2022

Parameterized multichannel Wiener filter (PMWF) is a linear filter that can control the trade-off between residual noise and signal distortion using the embedded parameter. To apply the PMWF to noisy inputs, accurate noise estimation is important and multichannel minima-controlled recursive averaging (MMCRA) is widely used. However, in the case of the MMCRA, the accuracy of noise estimation decreases when a directional interference is involved into the array inputs. Consequently, the performance of the PMWF is degraded. Therefore, we propose a noise power spectral density (PSD) estimation method for the PMWF in this paper. The proposed method is based on a consecutive process of eigenvalue decomposition on noisy input PSD, estimation of the target component contribution using directional information, and exponential weighting for improved estimation of the target contribution. For evaluation, four objective measures were compared with the MMCRA and we verify that the PMWF with the proposed noise estimation method can improve performance in environments where directional interfereces exist.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.368-376
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• 2006

This paper describes a Fcore_GenSim(Parameterized FFT Core Generation & Simulation Program), which can be used as an essential If(Intellectual Property) in various OFDM modem designs. The Fcore_Gensim is composed of two parts, a parameterized core generator(PFFT_CoreGen) that generates Verilog-HDL models of FFT cores, and a fixed-point FFT simulator(FXP_FFTSim) which can be used to estimate the SQNR performance of the generated cores. The parameters that can be specified for core generation are FFT length in the range of 64 ~2048-point and word-lengths of input/output/internal/twiddle data in the range of 8-b "24-b with 2-b step. Total 43,659 FFT cores can be generated by Fcore_Gensim. In addition, CBFP(Convergent Block Floating Point) scaling can be optionally specified. To achieve an optimized hardware and SQNR performance of the generated core, a hybrid structure of R2SDF and R2SDC stages and a hybrid algorithm of radix-2, radix-2/4, radix-2/4/8 are adopted according to FFT length and CBFP scaling.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.2
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• pp.82-88
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• 2005

A compensation scheme for a class of linearly parameterized systems is presented. The compensator consists of a typical linearizing control and an adaptive observer with integration type update law, which is based on Speed Gradient (SG) algorithm.. Instead of the intermediate functions of the compensation schemes suggested by other researchers, the proposed compensator is designed with some design functions which guarantee the growth, convexity, attainability, and pseudo gradient conditions in the update law. The scheme achieves the asymptotic stability of the tracking error and the boundedness of the estimation errors. A numerical example is given to demonstrate the validity of the proposed design.