• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.774-780
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• 2017

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.6
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• pp.335-344
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• 2014

As a kind of 2D spatial coordinate transform, image warping is a basic image processing technique utilized in various applications. Though image warping algorithm is composed of relatively simple operations such as memory accesses and computations of weighted average, real-time implementations on embedded vision systems suffer from limited computational power because the simple operations are iterated as many times as the number of pixels. This paper presents a real-time implementation of a look-up table(LUT)-based image warping using an FPGA. In order to ensure sufficient data transfer rate from memories storing mapping LUT and image data, appropriate memory devices are selected by analyzing memory access patterns in an LUT-based image warping using backward mapping. In addition, hardware structure of a parallel and pipelined architecture is proposed for fast computation of bilinear interpolation using fixed-point operations. Accuracy of the implemented hardware is verified using a synthesized test image, and an application to real-time lens distortion correction is exemplified.

• Proceedings of the KIEE Conference
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• 2006.11a
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• pp.198-200
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• 2006

This paper presents a development of an educational simulator of particle swarm optimization (PSO) and application for solving the test functions and economic dispatch (ED) problems with nonsmooth cost functions. A particle swarm optimization is one of the most powerful methods for solving global optimization problems. It is a population-based search algorithm and searches in parallel using a group of particles similar to other AI-based heuristic optimization techniques. In developed simulator, lecturers and students can select the functions for simulation and set the parameters that have an influence on PSO performance. To improve searching capability for ED problems, a crossover operation is proposed to the position update of each individual (CR-PSO). To verify the feasibility of CR-PSO method, numerical studies have been performed for two different sample systems. The proposed CR-PSO method outperforms other algorithms in solving ED problems.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.233-240
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• 2005

In this paper, AC electric vehicle propulsion system(Converter/Inverter) using high power semiconductor, IPM is proposed. 2-Parallel operation of two PWM converter is adopted for increasing capacity of system and the harmonic content is eliminated by the phase shaft between two PWM converters switching phase. VVVF inverter control is used a mixed control algorithm, where the vector control strategy at low speed region and slip-frequency control strategy at high speed region. The proposed propulsion system is verified by experimental results with a 1,350kW converter and 1,100kVA inverter with four 210kW traction motors.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.6
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• pp.313-319
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• 2019

Finite field operations have played an important role in error correcting codes and cryptosystems. Recently, the necessity of efficient computation processing is increasing for security in cyber physics systems. Therefore, efficient implementation of finite field arithmetics is more urgently needed. These operations include addition, multiplication, division and inversion. Addition is very simple and can be implemented with XOR operation. The others are somewhat more complicated than addition. Among these operations, multiplication is the most important, since time-consuming operations, such as exponentiation, division, and computing multiplicative inverse, can be performed through iterative multiplications. In this paper, we propose a multiplexer based parallel computation algorithm that performs Montgomery multiplication over finite field using redundant basis. Then we propose an efficient multiplexer based semi-systolic multiplier over finite field using redundant basis. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the AT complexity of the proposed multiplier is improved by approximately 19% and 65% compared to the multipliers of Kim-Han and Choi-Lee, respectively. Therefore, our multiplier is suitable for VLSI implementation and can be easily applied as the basic building block for various applications.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.87-93
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• 1989

Squared-error Pattern Clustering algorithm used in unsupervised pattern recognition and image processing application demands substantial processing time for operation of feature vector matrix. So, this paper propose the fast squared-error Pattern Clustering Processor using the Residue Number System which have been the nature of parallel processing and pipeline. The proposed Squared-error Pattern Clustering Processor illustrate satisfiable error rate for Cluster number which can be divide meaningful region and about 200 times faster than 80287 coprocessor from experiments result of image segmentation. In this result, it is useful to real-time processing application for large data.

• Proceedings of the KIEE Conference
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• 1998.07c
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• pp.908-910
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• 1998

Modern AC electric car has PWM(Pulse Width Modulation) -controlled converters, which give rise to higher harmonics. The current harmonics injected from AC electric car is propagated through power feeding circuit. As the feeding circuit is a distributed constant circuit composed of RLC, the capacitance of the feeding circuit and the inductance on the side of power system cause a parallel resonance and a magnification of current harmonics at a specific frequency. The magnified current harmonics usually brings about various problems. That is, the current harmonics makes interference in the adjacent lines of communications and the railway signalling system. Furthermore, in case it flows on the side of power system, not only overheating and vibration at the power capacitors but also wrong operation at the protective devices can occur. Therefore, the exact assessment of the harmonic current flow must be undertaken at design and planning stage for the electric traction systems. From these point of view, this study presents an approach to model and to analyse traction power feeding system focused on the amplification of harmonic current. The proposed algorithm is applied to a standard AT(Auto-transformer)-fed test system in which electric car with PWM-controlled converters is running.

• Proceedings of the KSR Conference
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• 1999.11a
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• pp.318-325
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• 1999

Modern AC electric car has PWM(Pulse Width Modulation)-controlled converters, which give rise to higher harmonics. The current harmonics injected from AC electric car is propagated through power feeding circuit, As the feeding circuit is a distributed constant circuit composed of RLC, the capacitance of the feeding circuit and the inductance on the side of power system cause a parallel resonance and a magnification of current harmonics at a specific frequency. The magnified current harmonics usually brings about various problems. That is, the current harmonics makes interference in the adjacent lines of communications and the railway signalling system. Furthermore, in case it flows on the side of power system, not only overheating and vibration at the power capacitors but also wrong operation at the protective devices can occur. Therefore, the exact assessment of the harmonic current flow must be undertaken at design and planning stage for the electric traction systems. From these point of view, this study presents an approach to model and to analyse traction power feeding system focused on the amplification of harmonic current The proposed algorithm is applied to a standard AT(Auto-transformer)-fed test system in which electric car with PWM-controlled converters is running.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.5
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• pp.357-363
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• 2021

Eco-friendly hybrid railroad propulsion system with fuel-cell and battery was suggested to reduce carbon dioxide gas and replace retired diesel railroads. Lithium-ion battery with high energy/power density and long lifetime is selected as the energy source at the battery side due to its excellent performance. However, the performance of lithium-ion batteries was affected by temperature, current rate, and operating condition. Temperature is known to be the most influential factor in changing battery parameters. In addition, appropriate thermal management is required to ensure the safe and effective operation of lithium-ion battery. Electro-thermal coupled model with varying parameter depends on temperature, and state-of-charge (SOC) is suggested to estimate battery temperature. The electric-thermal coupled model contains diffusion current using parameter identification by adaptive control algorithm when considering thermal diffusion effect. An experiment under forced convection was conducted using cylindrical cell and 18 parallel-connected battery module to demonstrate the method.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.3
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• pp.31-36
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• 2022

Recently, drones are being used in various fields, and drone technology is also developing. The risks of drones are increasing, then technology to detect drones is important. However, it is extremely difficult to detect and recognize drones due to the low level radar cross section of the commercial drones. In this paper, a signal processor structure that was mounted the miniaturized and light-weighted was designed. in order to process large amounts of data in real time, parallel processing was performed for each channel and an algorithm was applied to shorten the operation time in each step. As a test of verifing the detection performance through test, it was confirmed that the structure design works in real time.