• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 추계학술대회
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• pp.36-38
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• 2018

As the battery capacity requirement increases, battery cells are connected in a parallel configuration. However, the sharing current of each battery cell becomes unequal due to the imbalance between cell's impedance which results the mismatched states of charge (SOC). The conventional fixed-resistance balancing methods have a limitation in battery equalization performance and system efficiency. This paper proposes a battery equalization method based on dynamic resistance technique, which can improve equalization performance and reduce the loss dissipation. Based on the SOC rate of parallel connected battery cells, the switches in the equalization circuit are controlled to change the equivalent series impedance of the parallel branch, which regulates the current flow to maximize SOC utilization. To verify the method, operations of 4 parallel-connected 18650 Li-ion battery cells with 3.7V-2.6Ah individually are simulated on Matlab/Simulink. The results show that the SOCs are balanced within 1% difference with less power dissipation over the conventional method.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.50-52
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• 2019

Dynamic resistance equalization is a viable technique to balance SOC of cells in a parallel-connected battery configuration due to high equalization performance, simplicity and low-cost. However, an inappropriate design of the equalization resistor can degrade the equalization performance and increase the power loss. This paper proposes an optimization process to design the equalization resistors to minimize power loss and equalization error. The simulation results show that the optimally designed resistor significantly enhance the performance in comparison with the conventional fixed-resistor equalization.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.350-352
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• 2007

Modularized charge equalization converter for HEV lithium-ion battery cells is proposed in this paper, in which intra-module and inter-module charge equalization can be achieved at the same time. For intra-module charge equalization, the conventional flyback DC/DC converters of low power and small size are employed, in which all of the primary sides are coupled in parallel for selective charge of the specific under charged cell within the module. For inter-module charge equalization, the flyback DC/DC converters are also added, in which all the secondary windings are electrically linked in parallel for automatic charge balancing among the modules. An engineering sample of forty cells hiring the proposed cell balancing scheme is implemented and its experimental result shows that the proposed modularized charge equalization circuit has good cell balancing performance.

• 대한전자공학회논문지TC
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• 제49권7호
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• pp.32-38
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• 2012

다중경로 전파에 의한 수신 신호의 심벌간 간섭을 제거하기 위해, 두 오차 추정 함수를 사용하는 병렬 등화(parallel equalization) 알고리즘을 제안한다. 제안 알고리즘에서는 다치레벨 이차원 신호를 등가 이진 신호로 간주하고, 등화 초기에 효과적인 시그모이드 함수와 정상상태 성능이 우수한 임계 함수를 사용하여 각각 오차를 추정한다. 이때 두 오차 추정의 상대적 정확도에 따라 두 오차를 가중 처리하여 두 필터를 서로 다르게 갱신하도록 하였다. 결과적으로 결합된 두 필터의 출력이 최적한 값이 되도록 하였으며, 두 동작 모드를 완만하게 결합하는 효과로 등화 초기의 빠른 수렴과 정상상태에서의 낮은 오차 레벨을 동시에 달성하였다. 제안 알고리즘의 유용성을 모의실험을 통해 기존 방식과 비교, 검증하였다.

• 한국정보통신학회논문지
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• 제23권11호
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• pp.1377-1383
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• 2019

영상 품질 개선을 위해 사용되는 히스토그램 평활화 알고리즘은 하드웨어 회로로 구현되면 소프트웨어로 구현된 경우보다 작업 속도 면에서 성능이 훨씬 뛰어나다. FPGA를 이용한 히스토그램 평활화 회로 구현에 대부분의 최신 FPGA에 포함된 곱셈기 회로와 상당량의 SRAM을 이용하고, 파이프라인을 적용하면 히스토그램 평활화 회로의 전체적인 동작 성능을 높일 수 있다. 본 논문은 이와 같은 방법을 적용하여 8비트 심도를 갖는 흑백 영상에 대해 히스토그램 평활화 작업을 고속으로 수행 가능한 FPGA 구현 방법을 제안한다. 제안된 회로는 FIFO를 이용하여 한 개의 영상에 대한 평활화가 진행되는 동안 다음 영상에 대한 히스토그램 계산을 수행할 수 있다. FIFO를 이용한 일부 작업의 시간적 중첩과 내장된 곱셈기 회로 그리고 파이프라인 적용 효과로 회로의 전체적인 성능은 대략 매 클럭마다 한 개의 화소에 대해 히스토그램 평활화를 수행할 수 있다. 그리고 영상을 분할하여 히스토그램 평활화 작업의 일부를 병렬 처리하면 그 성능을 속도 면에서 거의 두 배로 향상할 수 있다.

• Journal of Power Electronics
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• 제9권3호
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• pp.472-480
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• 2009

In this paper, a charge equalization converter with parallel-connected primary windings of transformers is proposed. The proposed work effectively balances the voltage among Lithium-Ion battery cells despite each battery cell has low voltage gap compared with its state of charge (SOC). The principle of the proposed work is that the equalizing energy from all battery strings moves to the lowest voltage battery through the isolated dc/dc converter controlled by the corresponding solid state relay switch. For this research a prototype of four Lithium-Ion battery cells is optimally designed and implemented, and experimental results show that the proposed method has excellent cell balancing performance.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.274-276
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• 2008

This paper proposes an individual charge equalization converter using selective two current paths for series connected lithium-ion battery strings. In the proposed equalizer, a central equalization converter acting as a controllable current source is sequentially connected in parallel with individual batteries through an array of cell selection switches. A flyback converter with a modified rectifier realizes a controllable current source. A central equalization converter is shared by every battery cells through the cell selection switch, instead of a dedicated charge equalizer for each cell. With this configuration, although the proposed equalizer has one dc-dc converter, individual charge equalization can be effectively achieved for the each cell in the strings. Furthermore, since the proposed equalizer would not allocate the separated dc-dc converter to each cell, such that the implementation of great size reduction and low cost can be allowed. In this paper, an optimal power rating design guide is also employed to obtain a minimal balancing size while satisfying equalization requirements. A prototype for eight lithium-ion battery cells is optimally designed and implemented. Experimental results verify that the proposed equalization method has good cell balancing performance showing small size, and low cost.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.347-349
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• 2007

Charge equalization scheme for HEV lithium-ion battery system is proposed in this paper, where all the primary windings with in parallel bi-directional switches are coupled in series to provide the equalizing energy from the whole battery string to the specific under charged cells. Moreover, to realize minimized size of equalization circuit employing the proposed cell balancing scheme, the optimal power rating design rule according to equalization time and SOC distribution of imbalance is proposed. A prototype of HEV lithium-ion battery system of four cells shows the outstanding charge equalization performance while maintaining greatly reduced size of cell balancing circuit.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.256-258
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• 2007

A charge equalization converter with parallel-connected primary windings of transformers is proposed in digest. The proposed work effectively balance the voltage among Lithium-Ion battery cells despite each battery cell has low voltage gap compared with its SOC. The principle of the proposed work is that the equalizing energy from all battery strings moves to the lowest voltage battery through the isolated dc/dc converter controlled by the corresponding bi-directional switch. In this digest, a prototype of four Lithium-Ion battery cells is optimally designed and implemented, and experimental results show that the proposed method has excellent cell balancing performance.

• 제어로봇시스템학회논문지
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• 제6권6호
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• pp.492-499
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• 2000

In this paper, realization techniques of the parallel processing and the parallel network system for image processing are described. The parallel image processing system is constructed by the characterization of image processing and processor. Several problems are solved to achieve effective parallel processing and processor networking with the particular properties of image processing, which are reduction of communication quantity, equalization of load and delay depreciation on communication. A parallel image input device is developed for the flexible networking of parallel image processing. An abnormal region detection algorithm which is the basic function in machine vision is applied to evaluate the constructed parallel image processing system. The performance and effectiveness of the system are confirmed by experiments.