• Title/Summary/Keyword: Parallel device

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All Phase Discrete Sine Biorthogonal Transform and Its Application in JPEG-like Image Coding Using GPU

  • Shan, Rongyang;Zhou, Xiao;Wang, Chengyou;Jiang, Baochen
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.10 no.9
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    • pp.4467-4486
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    • 2016
  • Discrete cosine transform (DCT) based JPEG standard significantly improves the coding efficiency of image compression, but it is unacceptable event in serious blocking artifacts at low bit rate and low efficiency of high-definition image. In the light of all phase digital filtering theory, this paper proposes a novel transform based on discrete sine transform (DST), which is called all phase discrete sine biorthogonal transform (APDSBT). Applying APDSBT to JPEG scheme, the blocking artifacts are reduced significantly. The reconstructed image of APDSBT-JPEG is better than that of DCT-JPEG in terms of objective quality and subjective effect. For improving the efficiency of JPEG coding, the structure of JPEG is analyzed. We analyze key factors in design and evaluation of JPEG compression on the massive parallel graphics processing units (GPUs) using the compute unified device architecture (CUDA) programming model. Experimental results show that the maximum speedup ratio of parallel algorithm of APDSBT-JPEG can reach more than 100 times with a very low version GPU. Some new parallel strategies are illustrated in this paper for improving the performance of parallel algorithm. With the optimal strategy, the efficiency can be improved over 10%.

A Study on the Application of SFCL on 22.9 kV Bus Tie for Parallel Operation of Power Main Transformers in a Power Distribution System (배전계통에 전력용 변압기 병렬운전시 22.9 kV SFCL Bus Tie 적용방안에 관한 연구)

  • On, Min-Gwi;Kim, Myoung-Hoo;Kim, Jin-Seok;You, Il-Kyoung;Lim, Sung-Hun;Kim, Jae-Chul
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.1
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    • pp.20-25
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    • 2011
  • This paper analyzed the application of Superconducting Fault Current Limiter (SFCL) on 22.9 [kV] bus tie in a power distribution system. Commonly, the parallel operations of power main transformers offer a lot of merits. However, when a fault occurs in the parallel operation of power main transformer, the fault currents might exceed the interruption capacity of existing protective devices. To resolve this problem, thus, the SFCL has been studied as the fascinating device. In case that, Particularly, the SFCL could be installed to parallel operation of various power main transformers in power distribution system of the Korea Electric Power Corporation (KEPCO) on 22.9 [kV] bus tie, the effect of the resistance of SFCL could reduce the increased fault currents and meet the interruption capacity of existing protective devices by them. Therefore, we analyzed the effect of application and proposed the proper impedance of the R-type SFCL on 22.9 [kV] bus tie in a power distribution system using PSCAD/EMTDC.

Fast High-throughput Screening of the H1N1 Virus by Parallel Detection with Multi-channel Microchip Electrophoresis

  • Zhang, Peng;Park, Guenyoung;Kang, Seong Ho
    • Bulletin of the Korean Chemical Society
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    • v.35 no.4
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    • pp.1082-1086
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    • 2014
  • A multi-channel microchip electrophoresis (MCME) method with parallel laser-induced fluorescence (LIF) detection was developed for rapid screening of H1N1 virus. The hemagglutinin (HA) and nucleocapsid protein (NP) gene of H1N1 virus were amplified using polymerase chain reaction (PCR). The amplified PCR products of the H1N1 virus DNA (HA, 116 bp and NP, 195 bp) were simultaneously detected within 25 s in three parallel channels using an expanded laser beam and a charge-coupled device camera. The parallel separations were demonstrated using a sieving gel matrix of 0.3% poly(ethylene oxide) ($M_r$ = 8,000,000) in $1{\times}$ TBE buffer (pH 8.4) with a programmed step electric field strength (PSEFS). The method was ~20 times faster than conventional slab gel electrophoresis, without any loss of resolving power or reproducibility. The proposed MCME/PSEFS assay technique provides a simple and accurate method for fast high-throughput screening of infectious virus DNA molecules under 400 bp.

A Study on the Difference Method of Magnetic Resonance Signal Measurement when Using Multi-channel Coil and Parallel Imaging

  • Choi, Kwan-Woo;Lee, Ho-Beom;Son, Soon-Yong;Jeong, Mi-Ae
    • Journal of Magnetics
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    • v.22 no.2
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    • pp.220-226
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    • 2017
  • SNR (signal to ratio) is a criterion for providing objective information for evaluating the performance of a magnetic resonance imaging device, and is an important measurement standard for evaluating the quality of MR (Magnetic Resonance) image. The purpose of our study is to evaluate the correct SNR measurement for multi-channel coil and parallel imaging. As a result of research, we found that both T1 and T2 weighted images show the narrowest confidence interval of the method recommended by NEMA (The National Electrical manufacturers Association) 1 having a single measurement method, whereas the ACR (American College of Radiology) measurement method using a multi-channel coil and a parallel imaging technique shows the widest confidence interval. There is a significance in that we quantitatively verified the inaccurate problems of a signal to noise ratio using a ACR measurement method when using a multi-channel coil and a parallel imaging technique of which method does not satisfy the preconditions that researchers could overlook.

An Improved Hybrid Approach to Parallel Connected Component Labeling using CUDA

  • Soh, Young-Sung;Ashraf, Hadi;Kim, In-Taek
    • Journal of the Institute of Convergence Signal Processing
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    • v.16 no.1
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    • pp.1-8
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    • 2015
  • In many image processing tasks, connected component labeling (CCL) is performed to extract regions of interest. CCL was usually done in a sequential fashion when image resolution was relatively low and there are small number of input channels. As image resolution gets higher up to HD or Full HD and as the number of input channels increases, sequential CCL is too time-consuming to be used in real time applications. To cope with this situation, parallel CCL framework was introduced where multiple cores are utilized simultaneously. Several parallel CCL methods have been proposed in the literature. Among them are NSZ label equivalence (NSZ-LE) method[1], modified 8 directional label selection (M8DLS) method[2], and HYBRID1 method[3]. Soh [3] showed that HYBRID1 outperforms NSZ-LE and M8DLS, and argued that HYBRID1 is by far the best. In this paper we propose an improved hybrid parallel CCL algorithm termed as HYBRID2 that hybridizes M8DLS with label backtracking (LB) and show that it runs around 20% faster than HYBRID1 for various kinds of images.

Series tuned mass dampers in train-induced vibration control of railway bridges

  • Kahya, Volkan;Araz, Onur
    • Structural Engineering and Mechanics
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    • v.61 no.4
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    • pp.453-461
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    • 2017
  • This paper presents the series multiple tuned mass dampers (STMDs) to suppress the resonant vibrations of railway bridges under the passage of high-speed trains (HSTs). A STMD device consisting of two spring-mass-damper units connected each other in series is installed on the bridge. In solution, bridge is modeled as a simply-supported Euler-Bernoulli beam with constant cross-section, and vehicle is simulated as a series of moving forces with constant speed. By the assumed mode method, the governing equations of motion of the beam-TMD device coupled system traversed by a moving train are obtained. The optimum values for the parameters of the STMD device are obtained for the criterion based on the minimization of the maximum dynamic displacement of the beam at its midspan. Single TMD and multiple TMDs in parallel are also considered for demonstration of the STMD device's performance. The results show that STMDs are effective in bridge vibration suppression and robust to parameters' change in the main system and the absorber itself.

The Vertical Trench Hall-Effect Device Using SOI Wafer (SOI Wafer를 사용한 트렌치 구조의 수직 Hall 소자의 제작)

  • Park, Byung-Hwee;Jung, Woo-Chul;Nam, Tae-Chul
    • Proceedings of the KIEE Conference
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    • 2002.07c
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    • pp.2023-2025
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    • 2002
  • We have fabricated a novel vertical trench-Hall device sensitive to the magnetic field parallel to the sensor chip surface. The vertical trench-Hall device is built on SOI wafer which is produced by silicon direct bonding technology using bulk micromachining, where buried $SiO_2$ layer and surround trench define active device volume. Sensitivity up to 350 V/AT is measured.

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Magnetic Characteristics of an InSb Hall Device of Multilayerd Structure (다충구조 InSb 홀소자의 제작과 특성)

  • 이우선;김상용;서용진;박진성;김창일
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.8
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    • pp.681-687
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    • 2000
  • Magnetic Characteristics of an InSb hall device of multilayered structures were investigated. For the measurement of electrical properties of the hall device InSb thin films fabricated with series and parallel multilayers wee evaporated. Hall coefficient hall mobility carrier density and hall voltage were measured as a function of the intensity of magnetic field. We found that the XRD analysis of InSb thin film showed good properties at 20$0^{\circ}C$ 60 minutes. Resistance of ohmic contact was increased linearly due to increasing current. Hall voltages at 0.01 T showed 5$\times$10$^{-4}$ [V] and $1.5\times$10$^{-3}$ [V]. Some of device fabrication technique and analysis of magnetic characteristics were discussed.

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The Junction Termination Design Employing Shallow Trench and Field Limiting Ring for 1200 V-Class Devices (얕은 트렌치와 전계 제한 확산 링을 이용한 접합 마감 설계의 1200 V급 소자에 적용)

  • 하민우;오재근;최연익;한민구
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.53 no.6
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    • pp.300-304
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    • 2004
  • We have proposed the junction termination design employing shallow trench filled with silicon dioxide and field limiting ring (FLR). We have designed trenches between P+ FLRs to decrease the junction termination radius without sacrificing the breakdown voltage characteristics. We have successfully fabricated and measured improved breakdown voltage characteristics of the Proposed device for 1200 V-class applications. The junction termination radius of the proposed device has decreased by 15%-21% compared with that of the conventional FLR at the identical breakdown voltage. The junction termination area of the proposed device has decreased by 37.5% compared with that of the conventional FLR. The breakdown voltage of the proposed device employing 7 trenches was 1156 V, which was 80% of the ideal parallel-plane .junction breakdown voltage.

Characteristic Analysis of The Vertical Trench Hall Sensor using SOI Structure (SOI 구조를 이용한 수직 Hall 센서에 대한 특성 연구)

  • 이지연;박병휘
    • Journal of the Microelectronics and Packaging Society
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    • v.9 no.4
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    • pp.25-29
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    • 2002
  • We have fabricated a vertical trench Hall device which is sensitive to the magnetic field parallel to the sensor surface. The vertical trench Hall device has been built on SOI wafer which is produced by silicon direct bonding technology using bulk micromachining, where buried $SiO_2$ layer and surround trench define active device volume. Sensitivity up to 150 V/AT has been measured.

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