• 전기학회논문지
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• 제65권3호
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• pp.511-519
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• 2016

This paper is proposed control algorithm for the using thyristor of the parallel dual converter for Urban railway power supply in order to return the regenerative power generated by regenerative braking in urban railway train. Conventional control algorithm of Thyristor dual converter for urban railway power supply has voltage variation within a control range of hysteresis band. The purposed control algorithm of the parallel thyristor dual converter is to maintain a constant voltage without voltage variation in accordance with variable load through the Sequential mode change. And the control algorithm need calculating optimum initial firing angle to consider magnitude of the load current slope. For this purpose, Proposed algorithm for sequential conversion mode of the dual converter was verified by applying for the simulation.

• 전력전자학회논문지
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• 제26권3호
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• pp.205-213
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• 2021

Due to the advantage of reducing the voltage applied to the switch semiconductor, the input series and output parallel combination is widely used in systems with high input voltage and large output current. On the other hand, the LLC converter is widely used as a high-efficiency power converter, and when connected by ISOP combination, there is a possibility that input voltage imbalance may occur due to a mismatch of passive devices. To avoid damaging the switching device, this study analyzed the DC-link voltage imbalance of a high-capacity supply using an ISOP LLC converter. In addition, the case where DC-link unbalance control was applied and the case not applied was analyzed respectively. Based on this analysis, an initial start-up algorithm was proposed to prevent input power semiconductor device damage due to DC-link over-voltage. The effectiveness of the proposed algorithm has been verified through simulations and experiments.

• 전력전자학회논문지
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• 제12권5호
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• pp.400-408
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• 2007

본 논문에서의 병렬제어를 이용한 8kW급 대용량 영전압/영전류 풀 브릿지 DC-DC 컨버터의 개발 결과를 보인다. 본 논문에서는 효율적인 시스템 구성을 위해 4-병렬 단위 모듈 운전을 제안한다. 각 단위모듈은 위상 천이 풀 브릿지를 채택하고, ZVZCS 운전을 위해 간단한 보조 회로를 2차측에 추가하였다. ZCS를 위한 보조 회로 동작 로직은 환류 모드 구간에서 1차측 전류를 제거하도록 구현하였다. 또한 병렬 운전시의 출력 전류의 균등 제어를 위해 위상천이로직을 활용한 Charge Control 방식을 적용하였다. 전압 제어기는 DSP TMS320LF2406을 활용하여 4 모듈의 출력전류 및 출력전압을 A/D로 입력받아 구현하였다. 개발된 컨버터는 차량에 설치되는 고속 발전기용 전력 변환기에 장착되었으며, 구축된 모니터링 시스템으로 고속 발전기의 실제 운전 조건에서 데이터를 획득하여, 분석을 통해 그 성능을 입증하였다.

• Journal of Electrical Engineering and Technology
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• 제3권3호
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• pp.408-421
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• 2008

In this paper, the parallel operation for a FC generation system is introduced and designed in order to increase the capacity for the distributed generation of a proton exchange membrane fuel cell (PEMFC) system. The equipment is the type that is used by parallel operated PEMFC generation systems which have two PEMFC systems, two dc/dc boost converters with shared dc link, and a grid-connected dc/ac inverter for embedded generation. The system requirement for the purpose of parallel operated generation using PEMFC system is also described. Aspects related to the mechanical (MBOP) and electrical (EBOP) component, size, and system complexity of the distributed generation system, it is explained in order to design an optimal distributed generation system using PEMFC. The optimal controller design for the parallel operation of the converter is suggested and informative simulations and experimental results are provided.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.274-277
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• 2000

Power factor and harmonics are increasingly important for high speed train auxiliary block. This paper presents experimental results of the power factor and harmonic performance of four parallel PWM converter circuits under various supply and load conditions. For reducing harmonics the harmonic content is eliminated by the phase shift between four converters switching phase. Experimental results show the usefulness of the proposed method and applicability to PWM converter in auxiliary block of high speed train.

• 동력기계공학회지
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• 제6권3호
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• pp.64-70
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• 2002

A fast decoupled algorithm for time domain simulation of power electronics circuits is presented. The circuits can be arbitrarily configured and can incorporate feedback amplifier circuits. This simulation algorithm is performed for the input series output parallel connected 2 switch forward converter. Steady state and large signal transient responses due to a step load change are simulated. The simulation results are verified through experiments.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1229-1232
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• 2003

In this paper, The High-speed Low-power Analog-to-Digital Convener Archecture is proposed using the parallel S/H for High-speed operation. This technique can significantly reduce the sampling frequency per S/H channel. The Analog-to-Digital Converter is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology. The simulation result show that the proposed Analog-to-Digital Converter can be operated at 40Ms/s with 8-bit resolution and INL/DNL errors are +0.4LSB~-0.6LSB / +0.9LSB~-1.4LSB , respectively.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 전력전자학술대회 논문집
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• pp.455-459
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• 1998

In this paper input Series-Output Parallel connected converter configuration for high voltage power conversion applications is proposed and a control method to solve the problems of Input Series-Output Paralles connected converter configuration is introduced. In this configuration snubber circuit or voltage balancing controller that is necessary for the series connection of switching devices is not needed. The effectiveness of this proposed configuration is verified by simulation.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2006년도 전력전자학술대회 논문집
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• pp.140-142
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• 2006

This paper represents a digital parallel control of a synchronous buck converter using a digital signal processor (DSP). The digital PWM and load sharing controller is implemented in the DSP TMS320F2812 and the experimental results are provided to show the feasibility of the digital synchronous buck regulator.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.523-525
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• 2008

Novel zero-voltage switching(ZVS) dual inductor-fed DC-DC converter integrating a conventional dual inductor-fed boost converter(DIFBC) and a parallel bidirectional boost converter has been proposed. Most of current-fed type boost topologies including dual inductor schemes have crucial defects such as a high voltage spike on the main switch when it comes to turning off, an unattainable soft start-up due to the limited range of duty ratio, above 50%, and considerable switching losses due to the hard switching. By adding two auxiliary switches and an output capacitor on the conventional DIFBC, the proposed circuit can solve mentioned problems and improve the efficiency with simple methods. The operational principle and theoretical analysis of the proposed converter have been included. Experimental results based on a 42V input, 400V/1A output and 50kHz prototype are shown to verify the proposed scheme.