• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.3
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• pp.361-366
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• 2012

This paper proposes a low power capacitor cross-coupled 5.2 GHz band low noise amplifier(LNA) using the current-reused topology with the TSMC 0.18 ${\mu}m$ CMOS process. The proposed 5.2 GHz band LNA uses a capacitor cross-coupled $g_m$-boosting method for reducing current flow of circuit and a current-reused topology to decrease total power dissipation. The parallel LC networks are used to reduce size of spiral inductors. The simulation results show high gain of 17.4 dB and noise figure(NF) of 2.7 dB for 5.2 GHz.

• Journal of the Korea Computer Industry Society
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• v.2 no.3
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• pp.369-376
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• 2001

The optimization of resonator and laser power supply has been considered to be significant for improving the efficiency of a pulsed Nd:YAG laser system. We have proposed a new method of 3-mesh parallel sequential charge and discharge circuit as a laser power supply; more compact than conventional power supply, competitive in price, easy to control the laser power density according to various material processing, and equipped with the optimum reflectivity of output coupler. In this study, we could find that the maximum laser output was obtained by using 85% of reflectivity in the case of 50[W]-class. In addition using the power supply of new method, it's possible to charge each capacitor bank with a higher energy within the given charging time adopted a new method mentioned above; namely, we can allow each capacitor to have much more charging time and storage energy. So, higher laser output was obtained than conventional power supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.102-112
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• 2005

In this work, we developed fully integrated broadband MMIC chip set employing CSP(Chip Size Package) for K/Ka band applications. By utilizing an ACF for the RF-CSP, the fabrication process for the packaged amplifier MMIC could be simplified and made cost effective. $STO(SrTi_{3})$ capacitors were employed to integrate the DC biasing components on the MMIC, and LC parallel circuits were employed for DC feed and ESD protection. A pre-matching technique and RC parallel circuit were used to achieve a broadband matching and good stability fer the amplifier MMIC in K/Ka band. The amplifier CSP MMIC exhibited good RF performance over a wide frequency range in K/Ka band. This work is the first report of a fully integrated CSP amplifier MMIC successfully operating in the K/Ka band.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.397-409
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• 1993

This paper proposed the design methodology of the 8 bit binary parallel adder with carry book-ahead scheme via current-mode CMOS multivalued logic and simulated the proposed adder under $5{\mu}m$ standard IC process technology. The threshold conditions of $G_K$ and $P_K$ which are needed for m-valued parallel adder with CLA are evaluated and adopted for quaternary logic. The design of quaternary CMOS logic circuits, encoder, decoder, mod-4 adder, $G_K$ and $P_K$ detecting circuit and current-voltage converter is proposed and is simulated to prove the operations. These circuits are necessary for binary arithmetic using multivalued logic. By comparing with the conventional binary adder and the CCD-MVL adder, We show that the proposed adder cab be designed one look-ahead carry generator with 1-level structure under standard CMOS technology and confirm the usefulness of the proposed adder.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.3
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• pp.31-37
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• 2012

This paper presents an efficient hardware architecture to enable the high-speed Givens rotation-based QR decomposition. The proposed architecture achieves a highly parallel givens rotation process by maximizing the number of pivots selected for parallel zero-insertions. Sign-select lookahed (SSL)-CORDIC is also efficiently used for the high-speed givens rotation. The performance of QR decomposition hardware considerably increases compared to the conventional triangular systolic array (TSA) architecture. Moreover, the circuit area of QR decomposition hardware was reduced by decreasing the number of flip-flops for holding the pre-computed results during the decomposition process. The proposed QR decomposition hardware was implemented using TSMC $0.25{\mu}m$ technology. The experimental results show that the proposed architecture achieves up to 70 % speed-up over the TACR/TSA-based architecture for the $8{\times}8$ matrix decomposition.

• Aerospace Engineering and Technology
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• v.3 no.2
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• pp.11-19
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• 2004

A software-controlled unregulated bus system in which the main bus is directly connected to a battery and the duty-ratio for PWM switch is controlled by the on-board satellite software, is usually used for LEO satellites. This paper proposes a new power-stage circuit that can be available for modularization of a power regulator which is used at the software-controlled unregulated bus system satellite. And we analyze the proposed power-stage operation according to its operating modes and verify it by performing software simulation and hardware experiment using prototype. We construct a parallel-module converter which is composed of the proposed power-stage and perform experiment to verify modular characteristics of the proposed power-stage. Finally, we verify the usefulness of the proposed power-stage by comparing above results with those of a parallel-module converter made of conventional power-stage.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.36-46
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• 2017

The turbo code, an error correction code, needs a long decoding time since the same decoding process must be repeated several times in order to obtain a good BER performance. Thus, parallel processing may be used to reduce the decoding time, in which case there may be a memory contention that requires additional buffers. The QPP interleaving has been proposed to avoid such case, but there is still a possibility of memory contention when a decoder is constructed using the so-called double flow technique. In this paper, we propose an even-odd cross mapping technique to avoid memory conflicts even in decoding using the double-flow technique. This method uses the address generation characteristic of the QPP interleaving and can be used to implement the interleaving circuit between the decoding blocks and the LLR memory blocks. When the decoder implemented by applying the double flow and the proposed methods is compared with the decoder by the conventional MDF techniques, the decoding time is reduced by up to 32% with the total area increase by 8%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.4
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• pp.279-285
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• 2017

In this paper, the resonator with a parallel plate capacitor is newly proposed around sub-microwave frequency band and applied to earlobe for non-invasive glucose monitoring the human biological tissue. The capacitor including the earlobe as dielectric material is connected to inductive slot in the ground plane of the microstrip line. Based on the simulation, one port resonator circuit is designed and fabricated as a prototype. Three step glucose concentration levels(0, 250, 500 mg/dL) was tested, and its reflection coefficients($S_{11}$) were measured. Owing to high Q resonator more than 100, resonant frequency shift of about 9 MHz per glucose level of 250 mg/dL has been successfully measured. This proves that the proposed sensor is applicable to a blood glucose sensor.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.5B no.4
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• pp.366-373
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• 2005

This paper presents two new circuit topologies of the dc busline side active resonant snubber assisted voltage source high frequency link soft switching PWM full-bridge dc-dc power converters acceptable for either utility ac 200V-rms or ac 400V-rms input grid. These high frequency switching dc-dc converters proposed in this paper are composed of a typical voltage source-fed full-bridge PWM inverter, high frequency transformer with center tap, high frequency diode rectifier with inductor input filter and dc busline side series switches with the aid of a dc busline parallel capacitive lossless snubber. All the active switches in the full-bridge arms as well as dc busline snubber can achieve ZCS turn-on and ZVS turn-off transition commutation with the aid of a transformer leakage inductive component and consequently the total switching power losses can be effectively reduced. So that, a high switching frequency operation of IGBTs in the voltage source full bridge inverter can be actually designed more than about 20 kHz. It is confirmed that the more the switching frequency of full-bridge soft switching inverter increases, the more soft switching PWM dc-dc converter with a high frequency transformer link has remarkable advantages for its power conversion efficiency and power density implementations as compared with the conventional hard switching PWM inverter type dc-dc power converter. The effectiveness of these new dc-dc power converter topologies can be proved to be more suitable for low voltage and large current dc-dc power supply as arc welding equipment from a practical point of view.