• Proceedings of the KIEE Conference
• /
• 1999.07f
• /
• pp.2470-2474
• /
• 1999

The main drawback of parallel type active power filters (APFs) is the large capacity required for harmonic compensation. This paper evaluates the APF capacity requirement for harmonic/reactive power compensation for thyristor converter load. Theoretically achievable maximum power factor under partial load is evaluated. it is shown that the APF capacity can be considerably reduced by deliberately limiting the peak current, while maintaining the filtering performance with an acceptable total harmonic current level. the minimum capacity requirement of APF with current limiting is evaluated as a function of the firing angle of thyristor converter and short circuit ratio(SCR).

• Proceedings of the KIEE Conference
• /
• 2005.10b
• /
• pp.382-384
• /
• 2005

When a hearing aid' s user is listening through telephone or cellular phone, he/she usually suffers from severe electrical magnetic interference noise. It is because hearing aids amplify voice signal as well as background noise. A telecoil, an induction coil, is a possible solution for the problem. Because a telecoil has the characteristic of high pass filter, it has some problem of resulting increased high frequency noise. For solving this problem, we can use a capacitor connected with the telecoil in parallel. According to capacitance, receiving signal quality may change. In this paper, proper capacitor values for the best sound quality are investigated by experimental work.

• Proceedings of the KIEE Conference
• /
• 2005.10b
• /
• pp.551-553
• /
• 2005

When a hearing aid' s user is listening through telephone or cellular phone, he/she usually suffers from severe electrical magnetic interference noise. It is because hearing aids amplify voice signal as well as background noise. A telecoil, an induction coil, is a possible solution for the problem. Because a telecoil has the characteristic of high pass filter, it has some problem of resulting increased high frequency noise. For solving this problem, we can use a capacitor connected with the telecoil in parallel. According to capacitance, receiving signal quality may change. In this paper, proper capacitor values for the best sound quality are investigated by experimental work.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.125-125
• /
• 2010

The Hybrid Fault current limit combined the semiconductor switching components, for example IGBT, with mechanical fast switch reduced mechanical and thermal stress on electrical machines, for example circuit breaker, transformer, and so on, in the electric network. We had focused on reducing the voltage stress of the semiconductor switching components by the mechanical fast switch. As a result, we could dramatically reduce amount of semiconductor switching components only using parallel arrangement of them, not series.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.1
• /
• pp.234-243
• /
• 1995

An arry circuit is designed for parallel computation of vector-radix 2-D discrete cosine transform (VR-FCT) which is a fast algorithm of DCT. By using a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently implemented with high condurrency and local communication geometry. The proposed implementation features architectural medularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. The array core for (8$\times$8) 2-D DCT, which is designed usign ISRC 1.5.mu.m N-Well CMOS technology, consists of 64 PEs arranged in (8$\times$8) 2-D array and contains about 98,000 transistors on an area of 138mm$^{2}$. From simulation results, it is estimated that (8$\times$8) 2-D DCT can be computed in about 0.88 .mu.sec at 50 MHz clock frequency, resulting in the throughput rate of about 72${\times}10^[6}$ pixels per second.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.2
• /
• pp.205-216
• /
• 1996

In this paper we propose an efficient robust path delay fault test genration algorithm for detection of path delay faluts in combinational ligic circuits. In the proposed robust test genration approach, the testability measure is computed for all gates in the circuit under test and these computed values are used to genrate weighted random delay test vetors for detection of path delay faults. For genrated robust test vectors, we perform fault simulation on ISCAS '85 benchmark circuits using parallel pattern technqieus. The results indicate that the proposed test genration method not only increases the number of detected robust path delay faults but also reduces the time taen to genrate robust tests.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.6
• /
• pp.569-575
• /
• 2013

An improved non-quasi-static gate-source impedance model including a parallel RC block for short-channel MOSFETs is developed to simulate RF MOSFET input characteristics accurately in the wide range of high frequency. The non-quasi-static model parameters are accurately determined using the physical input equivalent circuit. This improved model results in much better agreements between the measured and modelled input impedance than a simple one with a non-quasi-static resistance up to 40GHz, verifying its accuracy.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.5
• /
• pp.415-422
• /
• 2013

In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in fault-tolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with self-checking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3- and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for self-checking than LUT with traditional Berger Coding scheme.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.32B no.3
• /
• pp.66-76
• /
• 1995

In this research, a mesh connected VLSI structure is proposed for the real time computation of the generalized Hough transform(GHT). The purpose of the research is to design a generalized Hough transformer that can be realized as a single chip processor. The GHT has been modified to yield a highly parallel structure consisting of simple processing elements(PEs) and communication networks. In the proposed structure, the GHT can be computed by first assigning an image pixel to a PE and performing shift and add operations. The result of the CAD circuit simulation shows that it can be computed in the time proportional to the number of pixels in the pattern. In addition to the Hough transformer, the peak detector has been designed to reduce 1)the number of the I/O operations between the transformer and the host computer and 2) the host computer's burden for peak detection by transmitting only the local peaks detected from the transformed accumulator. It is expected that the proposed single chip Hough transformer with peak detector makes a fast and inexpensive edge based object recognition systems possible for many industrial and military applications.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.31B no.9
• /
• pp.76-84
• /
• 1994

This paper presents a new high-performance VLSI architecture and VLSI implementation for full-search block matching algorithm. The proposed VLSI architecture has the feature of two directional parallel and pipeline processing, thereby reducing the PE idle time at which the direction of block matching operation within the search area is changed. Therfore, the proposed architecture is faster than the existing architectures under the same clock frequency. Based on HSPICE circuit simulation, it is verified that the implemented procesing element is operated successfully within 13 ns for 75 MHz operation.