• Proceedings of the KSR Conference
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• 2008.06a
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• pp.327-331
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• 2008

This paper dealt with high speed breaking method to parallel arcing in low-voltage systems. The proposed high speed breaking circuit consists of a Rogowski coil and an integrator, and operates with an earth leakage circuit breaker (ELCB). A parallel arcing state was simulated by a short circuit using stripped wires. In this test, we analyzed tripping characteristics of the circuit breaker by the length of wires from 5m to 30m. From the experimental results, we confirmed that the proposed method can break the parallel arcing within a few millisecond.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.1
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• pp.29-35
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• 2003

This paper presents a fault location algorithm when there are parallel circuits in power system networks. In transmission networks, a fault location method using the distribution factor of fault currents is introduced and in distribution networks a method using direct 3-phase circuit analysis is developed, because the distribution networks are unbalanced. The effect of parallel circuits in fault location is studied in this paper. The effect is important for the range of protecting zones of distance relay in transmission networks and fault location in distribution networks. The result of developed fault location algorithm shows high accuracy in the simulation that using the EMTP.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.42-49
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• 2000

In this paper, we propose the parallel ternary logic circuit design algorithm to DCG Property with 2$^n$ nodes. To increase circuit integration, one of the promising approaches is the use of multiple-valued logic(MVL). It can be useful methods for the realization of compact integrated circuit, the improvement of high velocity signal processing using parallel signal transmission and the circuit design algorithm to optimize and satisfy the circuit property. It is all useful method to implement high density integrated circuit. In this paper, we introduce matrix equation to satisfy given DCG with 2$^n$ nodes, and propose the parallel ternary logic circuit design process to circuit design algorithm. Also, we propose code assignment algorithm to satisfy for the given DCG property. According to the simulation result of proposed circuit design algorithm, it have the following advantage ； reduction of the circuit signal lines, computation time and costs.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.375-377
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• 2006

A Analog parallel processing-based Viterbi decoder which decodes PRML signal of DVD has been designed by CMOS circuit. The analog processing-based Viterbi decoder implements are functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The Analog parallel processing-based Viterbi decoding technology is applied for the PR(1,2,2,1) signal decoding of DVD. The benefits are low power consumption and less silicon consumption. In this paper, the comparison of the Analog parallel processing-based Viterbi Decoder which has a function of the error correction between Max operation and Average operation is discussed.

• Transactions on Electrical and Electronic Materials
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• v.5 no.1
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• pp.19-23
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• 2004

A novel method of high speed, accurate circuit simulation in 3-dimensional (3-D) parallel-plate capacitors is investigated. The basic concept of the circuit simulation methods is partial element equivalent circuit model. The three test structures of 3-D parallel-plate capacitors are fabricated by using multi-layer low-temperature co-fired ceramic (LTCC) process and their S-parameters are measured between 50 MHz and 5 GHz. S-parameters are converted to Y-parameters, for comparing measured data with simulated data. The circuit model parameters of the each building block are optimized and extracted using HSPICE circuit simulator. This method is convenient and accurate so that circuit design applications can be easily manipulated.

• Proceedings of the KIPE Conference
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• 1998.11a
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• pp.9-12
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• 1998

In this paper, the power factor correction circuit using a parallel drive method is proposed so that the high power inverter air-conditioner with 3[ph] compressor motor may obtain the cost down and the improved performance. The adequate design procedures are presented to reduce the material costs by eliminating the power factor improving LC filter and derating output capacitor and inverter switches. Using the determined components, the prototype circuit with 6[kW] power consumption is built and tested to verify the operation of the proposed circuit.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.268-273
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• 2002

In this paper, a new parallel multiplier circuit over $GF(2^m)$ has been proposed. The new multiplier is composed of polynomial multiplicative operation part and modular arithmetic operation part, irreducible polynomial operation part. And each operation has modular circuit block. For design the new proposed circuit, it develop generalized equations using frame each operation idea and show a example for $GF(2^m)$.

• Proceedings of the KIEE Conference
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• 2002.07a
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• pp.169-171
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• 2002

The western route of KEPCO's 765kV transmission line has been tentatively operating as 345kV voltage before commercial operation. After finishing the test operation of 765kV substation in 2002. KEPCO decided to operate the 765kV line for commercial operation. During the applying of 765kV voltage to the transmission line, double circuit transmission line will be operated with two voltage grades of 765kV and 345kV. Because the earthing switch is installed on both end of transmission line, we had estimated the electrostatic induction voltage and electromagnetic induction current before the line energizing in order to confirm the ratings of earthing switch. The induced voltage and current is very important for the maintenance of parallel circuit. This paper describes the simulation study of electrical phenomena such as electrostatic induction voltage from the parallel line and electromagnetic induction current from the parallel circuit. The transmission line model was developed by EMTP (Electro-Magnetic Transient Program).

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.128-133
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• 2006

This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.7
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• pp.1059-1065
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• 2017

In this paper, the energy harvester with a piezoelectric materials is modeled as the electric equivalent circuit, and performances of a standard DC method and a Parallel-SSHI method are verified through experiment under variable force and load conditions. Piezoelectric generator consists of mass, damper and spring constant, and it is modeled by electrical equivalent circuit with RLC components. Standard DC and Parallel-SSHI are used as power conversion methods, and standard DC consists of full-bridge rectifier and smoothing capacitor. Parallel-SSHI method is composed of L-C resonant circuit, zero-crossing detector and full-bridge rectifier. In case of simulation under $100k{\Omega}$ load condition, the harvested power is $500{\mu}W$ in Standard DC and $670{\mu}W$ in Parallel-SSHI, respectively. In experiment, the harvested power under $100k{\Omega}$ load condition is $420{\mu}W$ in standard DC and $602{\mu}W$ in Parallel-SSHI. Harvested power of Parallel-SSHI is improved by approximately 40% more than that of standard DC method.