• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.378-380
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• 2006

A high speed Analog parallel processing-based Viterbi decoder with a circularly connected 2D analog processing cell array is proposed. It has a 2D parallel processing structure in which an analog processing cell is placed at each node of trellis diagram is connected circulary so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error corrections, has a shorter latency and requires no path memories. In this parer, the performance of error correction as a reference position with the Analog parallel processing-based Viterbi decoder is testd via the software simulation

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.144-147
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• 2005

This paper is proposed an 8$\times$8 bit parallel multiplier for low power consumption. The 8$\times$8 bit parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing tile previous works, this circuit is reduced the power consumption rate of 8.2% and the power-delay-product of 11.1%. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.35$\{\mu}m$ standard CMOS process.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.269-272
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• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

• 조명전기설비학회논문지
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• 제16권4호
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• pp.15-21
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• 2002

본 논문에서는 동적 전류분담 인덕터를 이용한 ZVT 풀 브리지 DC/DC 컨버터의 병렬운전 특성을 해석하였다. 기존의 경우 CT(Current Transformer)를 사용하여 각 단위 컨버터 전류의 크기를 감지하여, 제어회로에서 각 컨버터에 균등한 전류 배분을 하는 방법을 사용하였으나, 본 연구에서는 동적 전류분담 인덕터를 사용함으로써 병렬운전하는 두 대의 풀 브리지 컨버터의 전류분배를 위한 제어회로를 비교적 단순하게 하였다. 동시에 ZVT회로를 이용하여 컨버터의 효율을 향상시켰으며 스위칭소자로서 IGBT를 사용하여 2[㎾]급 시작품을 제작, 50[KHz]에서 실험하였다.

• Journal of Power Electronics
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• 제16권2호
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• pp.769-777
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• 2016

This work focuses on current sharing between punch-through insulated gate bipolar transistors (IGBTs) connected in parallel and evaluates the mechanisms that allow overall current balancing. Two different control strategies are presented. These strategies are based on the modification of transistor gate-emitter control voltage V_GE by using an active gate driver circuit. The first strategy relies on the calculation of the average value of the current flowing through all parallel-connected IGBTs. The second strategy is proposed by the authors on the basis of a current cross reference control scheme. Finally, the simulation and experimental results of the application of the two current sharing control algorithms are presented.

• 대한전기학회논문지:전력기술부문A
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• 제53권3호
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• pp.168-174
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• 2004

This paper describes a new fault location algorithm based on the voltage equation at the relaying point using 6-phase current for untransposed 765㎸ parallel transmission lines. The proposed method uses the voltage and current collected at only the local end. By means of 3-phase circuit analysis theory to compensate the mutual coupling effects between parallel lines, the fault location is derived. The fault distance is determined by solving the 2nd distance equation based on KVL(Kirchhoff's Voltage Law). Extensive simulation results using EMTP(Electromagnatic Transients Program) have verified that the error of the fault location achieved is up to 4.56(%) in untransposed parallel transmission lines.

• 설비공학논문집
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• 제14권11호
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• pp.923-930
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• 2002

Cooling characteristics of a parallel channel with protruding heat sources using convection and conduction heat transfer are studied numerically. A two-dimensional model has been developed for numerical prediction of transient, compressible, viscous, laminar flow, and conjugate heat transfer between parallel plates with uniform block heat sources. The finite volume method is used to solve the problem. The assembly consists of two channels formed by two covers and one printed circuit board which has three uniform heat source blocks. Six different cooling methods are considered to find out the most efficient cooling method in a given geometry and heat sources. The velocity and temperature fields of cooling medium, the temperature distribution along the block surface, and the maximum temperature in each block are obtained. The results are compared to examine the cooling characteristics of the different cooling methods.

• Journal of Electrical Engineering and Technology
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• 제9권4호
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• pp.1137-1144
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• 2014

A parallel-feeding AC traction power system increases the power supply capacity and decreases voltage fluctuations, but the circulating power flow caused by the phase difference between the traction substations prevents the system from being widely used. A circuit analysis shows that the circulating power flow increases almost linearly as the phase difference increases, which adds extra load to the system and results in increased power dissipation and load unbalance. In this paper, we suggest a phase shifter for the parallel-feeding AC traction power system. The phase shifter regulates the phase difference and the circulating power flow by injecting quadrature voltage which can be obtained directly from the Scott-connection transformer in the traction substation. A case study involving the phase shifter applied to the traction power system of a Korean high-speed rail system shows that a three-level phase shifter can prevent circulating power flow while the phase difference between substations increases up to 12 degrees, mitigate the load unbalance, and reduce power dissipation.

• 산업경영시스템학회지
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• 제27권4호
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• pp.141-146
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• 2004

This research considers the problem of scheduling jobs on unrelated parallel machines with a common due date. The objective is to minimize the total absolute deviation of job completion times about the common due date. This problem is motivated by the fact that a certain phase of printed circuit board manufacturing and other production systems is bottleneck and the processing speeds of parallel machines in this phase are different for each job. A zero-one integer programming formulation is presented and two dominance properties are proved. By these dominance properties, it is shown that the problem is reduced to asymmetric assignment problem and is solvable in polynomial time.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.97-100
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• 1999

AC to DC single phase PWM converter for traction application requires rated high power and voltage. Therefor, series or parallel operation converters are necessary with considering the limitation of the power device specification. This paper compares the characteristic between two parallel operation of conventional PWM converter and Single phase three level converter about comparison of power circuit, cooling system control method and harmonic current by computer simulation.