• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.24-30
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• 2003

This study focuses on the arithmetical methodology and hardware implementation of low system-complexity A $B^2$＋C operator over GF(2$^{m}$ ) using the irreducible AOP of degree m. The proposed parallel-in parallel-out operator is composed of CS, PP, and MS modules, each can be established using the array structure of AND and XOR gates. The proposed multiplier is composed of (m＋1)$^2$ 2-input AND gates and (m＋1)(m＋2) 2-input XOR gates. And the minimum propagation delay is $T_{A}$ ＋(1＋$\ulcorner$lo $g_2$$^{m}$ $\lrcorner$) $T_{x}$ . Comparison result of the related A $B^2$＋C operators of GF(2$^{m}$ ) are shown by table, It reveals that our operator involve more lower circuit complexity and shorter propagation delay then the others. Moreover, the interconnections of the out operators is very simple, regular, and therefore well-suited for VLSI implementation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.3 s.118
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• pp.257-264
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• 2007

In this paper, we have designed and fabricated a wide-band and high gain antenna which can integrate a standard of IEEE 802.1la$(5.15\sim5.25\;GHz,\;5.25\sim5.35\;GHz,\;5.725\sim5.825\;GHz)$. We inserted a parallel dual slot into a rectangular patch to have wide-band, and we offset an element of capacitance from the slot by using coaxial probe feeding method. We also designed a converter of $\lambda_g/4$ impedance with taper type line so that wide-band impedance can be matched easily. We finally designed structure with $2\times2$ array in order to improve the antenna gain, and the final fabricated antenna could have a good return loss(Return loss$\leq$-10 dB) and a high gain(over 13 dBi) at the range of $5.01\sim5.95\;GHz(B/W\doteqdot940\;MHz)$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.510-520
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• 2011

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and compose the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells that have a mod(3) addition gate and a mod(3) multiplication gate. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Bulletin of the Korean Chemical Society
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• v.10 no.2
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• pp.177-184
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• 1989

The structure of cholesteryl isobutyrate, $(CH_3)_2CHCOOC_{27}H_{45}$, was determined by single crystal X-ray diffraction methods. Cholesteryl isobutyrate crystallized monoclinic space group $P2_1$, with a = 15.115 (8)${\AA}$, b = 9.636 (5)${\AA}$, c = 20.224 (9)${\AA}$, ${\beta}$ = 93.15 (5)$^{\circ}$, z = 4, $D_c = 1.03 g/cm^3 $and Dm= 1.04 g/$cm^3$. The intensity data were measured for the 3417 reflections, within $sin{\theta}/{\lambda} = 0.59{\AA}^{-1}$, using an automatic four-circle diffractometer and graphite monochromated Mo-$K_{\alpha}$ radiation. The structure was solved by fragment search Patterson methods and direct methods and refined by full-matrix least-squares methods. The final R factor was 0.129 for 2984 observed reflections. The two symmetry-independent molecules (A) and (B) are almost fully extended. The molecules are in antiparallel array forming monolayers with thickness $d_{100}$ = 15.2${\AA}$, and molecular long axes are nearly parallel to the [$\bar{1}$01] directions. The two distinct molecules form separate stacks with almost the same orientations, but with differing degrees of steroid overlap. Thers is a close packing of cholesteryl groups within the monolayers. The packing type is similar to those of cholesteryl hexanoate and cholesteryl oleate.

• Journal of the Korea Knowledge Information Technology Society
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• v.12 no.4
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• pp.539-550
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• 2017

In this paper, we designed, fabricated and tested an UHF band cylindrical dipole array antenna. In the proposed antenna, cylindrical dipoles were vertically arranged in four stages. A parallel structure feeding circuit was installed inside the cylindrical dipole and mounted so as to be broadband matching. The feeding circuit was installed at the center of the cylindrical dipole to optimize the gain flatness characteristic of the azimuth direction omnidirectional radiation pattern. Minimizing the difference between the signals branched from the feeding circuit and realizing the symmetry of the radiation pattern. The required specifications are more than 11.2% bandwidth in UHF band, above 6dBi antenna gain, standing wave ratio of 2:1 or less, less than ${\pm}1dB$ gain flatness in azimuth radiation pattern, more than 13 degrees in elevation radiation pattern of 3dB beamwidth. We confirmed the possibility of implementation through M&S and verified the result of M&S through production and testing. The test results are 11.2% bandwidth in the UHF band, 6.30 to 8.31 dBi gain, 1.53:1 standing wave ratio or less, within ${\pm}0.2dB$ gain flatness in the azimuth radiation pattern, elevation radiation pattern of 3dB beam width was 15.62 to 15.84 degrees. The test result meets all requirements specifications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.853-859
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• 2007

This paper presents a microstrip patch array antenna having transmission feed and reception feed for satellite communication in the Ku band. In this paper, the element of the patch array antenna is a three-stacked structure consisting of one radiation patch and two parasitic patches for high gain and wide bandwidth characteristics. To obtain higher gain, the unit elements are expanded into a $1{\times}8$ may using a mixture of series and parallel feeds. The proposed antenna has horizontal polarization for the Rx band and vertical polarization for the Tx band. To verify the practicality of this antenna, we fabricated a three-stacked patch array antenna and measured its performance. The gain of the array antenna in the Rx and Tx bands exceeds 17 and 18 dBi, respectively. The impedance bandwidth is over 10 % in both bands. The cross-polarization level is below -25 dB, and the sidelobe level is below -9.4 dB.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.1
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• pp.91-96
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• 2008

In this paper, a monopulse fled for three mode $2{\times}2$ array feed horn antenna was designed. Gain of single feed was 8.25dB. Increasing property of gain and rectangular waveguide and reflection of free space is decreased because it has structure extending to electric plane at connected part from transformation to free space. When fled port1 and port2 is placed vertically and thickness of aperture hem is reduced, isolation is satisfied with property of lower -25dB. Also, at higher frequency, it is confirmed that isolation is improved. Combination of electric field occurs less influence because port1 and port3 is placed horizontally and distribution of electric field is connected to parallel. However, because of combination of electric field, it is more improved from 2dB to 6dB than isolation of port1 and port2. Direct combination occult less effect at port1 and port4 than effect of port2 and port3, it is lower -35dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1970-1982
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• 1993

This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) fast discrete cosine transform (VR-FCT), and its VLSI implementation. By mapping the 2-D VR-FCT onto a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently importanted with high concurrency and local communication geometry. The proposed array algorithm features architectural modularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required, which is invitable in the conventional row-column decomposition approach. It has the time complexity of O(N+Nnzp-log2N) for (N*N) 2-D DCT, where Nnzd is the number of non-zero digits in canonic-signed digit(CSD) code, By adopting the CSD arithmetic in circuit desine, the number of addition is reduced by about 30%, as compared to the 2`s complement arithmetic. The computational accuracy analysis for finite wordlength processing is presented. From simulation result, it is estimated that (8*8) 2-D DCT (with Nnzp=4) can be computed in about 0.88 sec at 50 MHz clock frequency, resulting in the throughput rate of about 72 Mega pixels per second.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.5
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• pp.29-36
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• 2004

This study focuses on the arithmetical methodology and hardware implementation of low-system-complexity multiplier over GF(2$^{m}$ ) using the trinomial of degree a The proposed parallel-in parallel-out operator is composed of MR, PP, and MS modules, each can be established using the regular array structure of AND and XOR gates. The proposed multiplier is composed of $m^2$ 2-input AND gates and $m^2$-1 2-input XOR gates, and the propagation delay is $T_{A}$+(1+[lo $g_2$$^{m}$ ]) $T_{x}$ . Comparison result of the related multipliers of GF(2$^{m}$ ) are shown by table, it reveals that our operator involve more regular and generalized then the others, and therefore well-suited for VLSI implementation. Moreover, our multiplier is more suitable for any other GF(2$^{m}$ ) operational applications.s.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.103-108
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• 2016

In communication systems the solution of the problem of maximizing the mutual information between the input and output of a channel composed of several subchannels under total power constraint has a waterfilling structure. OFDM and MIMO can be decomposed into parallel subchannels with CSI. Waterfilling solves the problem of optimal power allocation to these subchannels to achieve the rate approaching the channel capacity under total power constraint. In waterfilling, more power is alloted to good channels(high SNR) and less or no power to bad channels to increase the rate of good channels, resulting in channel capacity. Waterfilling finds the exact water level satisfying the power constraint employing an iterative algorithm to estimate and update the water level. In this process computation of partial sums of inverse of square of subchannel gain is repeatedly required. In this paper we reduced the computation time of waterfilling algorithm by replacing the partial sum computation with reference to an array which contains the precomputed partial sums in initialization phase.