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A Study on the Hardware Architecture of Trinomial $GF(2^m)$ Multiplier  

변기영 (인하대학교 UWB-IT 연구센터)
윤광섭 (인하대학교 전자전기공학부)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.41, no.5, 2004 , pp. 29-36 More about this Journal
Abstract
This study focuses on the arithmetical methodology and hardware implementation of low-system-complexity multiplier over GF(2$^{m}$ ) using the trinomial of degree a The proposed parallel-in parallel-out operator is composed of MR, PP, and MS modules, each can be established using the regular array structure of AND and XOR gates. The proposed multiplier is composed of $m^2$ 2-input AND gates and $m^2$-1 2-input XOR gates, and the propagation delay is $T_{A}$+(1+[lo $g_2$$^{m}$ ]) $T_{x}$ . Comparison result of the related multipliers of GF(2$^{m}$ ) are shown by table, it reveals that our operator involve more regular and generalized then the others, and therefore well-suited for VLSI implementation. Moreover, our multiplier is more suitable for any other GF(2$^{m}$ ) operational applications.s.
Keywords
finite field; trinomial; standard basis; $GF(2^m)$ multiplier; modular reduction;
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