• Journal of Korean Society of Industrial and Systems Engineering
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• v.12 no.20
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• pp.47-53
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• 1989

This paper presents an algorithm CAPFACT to evaluate the reliability of a capacitated two terminal network such as a communication network, a power distribution network, and a pipeline network. The network is good(working) if and only if it is possible to transmit successfully the required system capacity from one specified terminal to the other. This paper defines new Capacitated series-parallel reduction to be applied to a series-parallel structure of the network. New Capacitated factoring method is applied to a non-series-parallel structure. The method is based on the factoring theorem given by Agrawal and Barlow. According to the existing studies on the reliability evaluation of the network that the capacity is not considered, the factoring method using reduction is efficient. The CAPFACT is more efficient than Aggarwal algorithm which enumerated and combined the paths. The efficiency is proved by the result of testing the number of operations and cpu time on FORTRAN compiler of VAX-11/780 at Hanyang University.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.473-473
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• 2000

This paper presents the 2-bit parallel algorithmic ADC using current mode for parallel method algorithm. It is operated by parallel conversion, 2-bit at each moment, and increase bit numbers by serial connection. The circuit operates in current mode. The comparison ratio can be controlled while working under mode operation. The circuit design used 0.8 ${\mu}{\textrm}{m}$ CMOS technology which capable to convert 2-bit in 50 ns, power consumed 0.786 nW, with input current 0-50 mA from 3V single supply. From simulation testing, the conversion rate is much faster than other method.

• Journal of Information Processing Systems
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• v.8 no.2
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• pp.301-314
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• 2012

In this paper, two new approaches to align English-Arabic sentences in bilingual parallel corpora based on the Multi-Class Support Vector Machine (MSVM) and the Hidden Markov Model (HMM) classifiers are presented. A feature vector is extracted from the text pair that is under consideration. This vector contains text features such as length, punctuation score, and cognate score values. A set of manually prepared training data was assigned to train the Multi-Class Support Vector Machine and Hidden Markov Model. Another set of data was used for testing. The results of the MSVM and HMM outperform the results of the length based approach. Moreover these new approaches are valid for any language pairs and are quite flexible since the feature vector may contain less, more, or different features, such as a lexical matching feature and Hanzi characters in Japanese-Chinese texts, than the ones used in the current research.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.534-535
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• 2014

This paper proposes parallel operation of multi function rapid-charger with an active power filter. Rapid-charger can be installed in public institutions or mart parking lot. But conventional charger has disadvantage that it can not be used as the active power filter in charging mode with only one charger. So using 3-parallel operation, effective mode transfer between battery charging and APF function can obtain effect of harmonic compensation and improving the utilization of the charger.

• International journal of advanced smart convergence
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• v.8 no.4
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• pp.194-199
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• 2019

As the performance of the system increases, more parallelized data is being processed than single processing of data. Today's cpu structure has been developed to leverage multicore, and hence data processing methods are being developed to enable parallel processing. In recent years desktop cpu has increased multicore, data is growing exponentially, and there is also a growing need for data processing as artificial intelligence develops. This neural network of artificial intelligence consists of a matrix, making it advantageous for parallel processing. This paper aims to speed up the processing of the system by using raspberrypi to implement the cluster building and parallel processing system against the backdrop of the foregoing discussion. Raspberrypi is a credit card-sized single computer made by the raspberrypi Foundation in England, developed for education in schools and developing countries. It is cheap and easy to get the information you need because many people use it. Distributed processing systems should be supported by programs that connected multiple computers in parallel and operate on a built-in system. RaspberryPi is connected to switchhub, each connected raspberrypi communicates using the internal network, and internally implements parallel processing using the Message Passing Interface (MPI). Parallel processing programs can be programmed in python and can also use C or Fortran. The system was tested for parallel processing as a result of multiplying the two-dimensional arrangement of 10000 size by 0.1. Tests have shown a reduction in computational time and that parallelism can be reduced to the maximum number of cores in the system. The systems in this paper are manufactured on a Linux-based single computer and are thought to require testing on systems in different environments.

• Journal of Korean Society for Quality Management
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• v.26 no.2
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• pp.27-38
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• 1998

Consider a life testing experiment in which multiple two-component shared parallel systems are put on test, and the test is terminated at a specified number of system failures. The bivariate data obtained from such a system-level life testing can be classified into three classes: 1) the case of failed two components with known failure times, 2) the case of censored two components, and 3) the case of one censored component and the other failed component of which the failure time might be known or unknown. Under this censoring scheme and the assumption of Freund's bivariate exponential life distribution, the maximum likelihood estimators are obtained. Results of comparative studies based on Monte Carlo simulation are presented.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.111-121
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• 1994

This paper proposes a memory testable code called MTA(Memory TestAble) code which is based on error correcting code technique for testing functional faults in semiconductor memories. The characteristics of this code are analyzed and compared with those of conventional codes. The developed decoding technique for this code can reduce the decoder circuits up to 70% and obtain two-times faster decoding speed than other codes such as hamming code or Hsiao code. The MTA code is eccectively applicable to parallel testing of semiconductor memories because it has the same information length and parity length. It can detect from single error functional faults to triple error in semiconductor memories.

• Journal of the Korean Data and Information Science Society
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• v.18 no.3
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• pp.637-644
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• 2007

We consider a life testing experiment in which several two component shared parallel system are put on test, and the test is terminated at a pre-designed experiment. The bivariate data obtained from such a system level life testing can be classified into three cases: (1) the case of failed two components with known failure times, (2) the case of one censored component and the other failed component of which the failure time might be known or unknown, (3) the case of censored two components. In this paper, the maximum likelihood estimators of parameters for Block and Basu bivariate exponential model under above censoring scheme are obtained and the results of comparative studies are presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.33-40
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• 2008

As the speed of memory is improved vey fast the advanced test equipments are needed to test the ultra-high speed memory devices efficiently. It is necessary to develop the Algorithmic Pattern Generator (ALPG) that tests fast memory devices effectively using the instructions that testers want to use. In this paper, we propose a new parallel ALPG for the ultra-high speed memory testing. The proposed ALPG can generate patterns for fast memory devices at high speed using manual instructions by the Instruction Analyzer.

• Journal of Information Processing Systems
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• v.6 no.4
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• pp.537-552
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• 2010

Software Debugging is the most time consuming and costly process in the software development process. Many techniques have been proposed to isolate different faults in a program thereby creating separate sets of failing program statements. Debugging in parallel is a technique which proposes distribution of a single faulty program segment into many fault focused program slices to be debugged simultaneously by multiple debuggers. In this paper we propose a new technique called Faulty Slice Distribution (FSD) to make parallel debugging more efficient by measuring the time and labor associated with a slice. Using this measure we then distribute these faulty slices evenly among debuggers. For this we propose an algorithm that estimates an optimized group of faulty slices using as a parameter the priority assigned to each slice as computed by value of their complexity. This helps in the efficient merging of two or more slices for distribution among debuggers so that debugging can be performed in parallel. To validate the effectiveness of this proposed technique we explain the process using example.