• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1424-1429
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• 2003

In this paper, the design method of sliding mode control (SMC) system for SISO linear system is discussed. First, we consider the similarity between the design method of sliding mode hyper plane using the strict positive realness and the characteristics of zeros of feedback system and the design method of simple adaptive control. Based on such a consideration, we propose the new design method of SMC system using parallel dynamic compensator. As a result, SMC system can be constructed only with the derivative of output signal for controlled plant. The performance of SMC system designed by proposed method is confirmed through the numerical example.

• 로봇학회논문지
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• 제7권2호
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• pp.101-112
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• 2012

It is well-known that when singularities are located within the workspace of the parallel mechanism (PM), the usefulness of its workspace is significantly deteriorated. To handle this problem, we suggest an optimal design method which leads to more useful and larger workspace of the PM by taking its singularity locations into consideration in design process. Kinematic models of three selected planar PMs, a 5R type PM, a 3-RPR type planar PM, and a 3-RRR type planar PM, are derived via screw theory and their singularity analyses are conducted. Then workspace optimal designs for those three PMs are conducted to verify that the suggested design method leads more useful and larger workspace in which deterioration by singularity is minimal.

• 대한전자공학회논문지
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• 제26권10호
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• pp.1518-1527
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• 1989

We proposed a technique to design a multimicrocomputer system for real-time parallel processing with an interconnection network which has good network latency time. In order to simplify the performance evaluation and the design procedure under the hard real-time constraints we defined network latency time which takes into account the queueing delays of the networks. We designed a dynamic interconnection network following the proposed technique, and the simulation results show that we can easily estimate the multimicrocomputer system's approximate performance using the defined network latency time before the actual design, so this definition can help the efficient design of the real-time parallel processing systems.

• 제어로봇시스템학회논문지
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• 제9권1호
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• pp.63-72
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• 2003

A new 6-DOF parallel haptic device is proposed. Many existing haptic devices require large power due to having floating actuator and also have small workspaces. The proposed new mechanism can generate 6-DOF reflecting force. This device is relatively light by employing non-floating actuators and has large workspace. Kinematic analysis and kinematic optimal design is performed for this mechanism. Dexterous workspace, global isotropic index, and global maximum force transmission ratio are considered as kinematic design indices. To deal with such multi-criteria optimization problem. composite design index is employed. For the given operational specifications, actuator sizing for this mechanism is also carried out.

• 스마트미디어저널
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• 제11권9호
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• pp.39-46
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• 2022

The WK-recursive network proposed by Vecchia and Sanges[1] is widely used in the design and implementation of local area networks and parallel processing architectures. It provides a high degree of regularity and scalability, which conform well to a design and realization of distributed systems involving a large number of computing elements. In this paper, the routing of a message is investigated on the WK-recursive network, which is key to the performance of this network. We present an efficient shortest path algorithm on the WK-recursive network, which is simpler than Chen and Duh[2] in terms of design complexity.

• Journal of Information Display
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• 제2권2호
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• pp.1-6
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• 2001

A $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with a new integrated 8-bit parallel-serial digital data driver was proposed and designed. For high resolution, the proposed parallel-serial digital driver used serial video data rather than parallel ones. Thus, digital circuits for driving one column line could be integrated within very small width. The parallel-serial digital data driver comprised of shift registers, latches, and serial digital-to-analog converters (DAC's). We designed a $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with integrated 8-bit parallel-serial digital data drivers by a circuit simulator which has physical-based analytical model of poly-Si TFT's. The fabricated shift register well operated at 2 MHz and $V_{DD}$=10V and the fabricated poly-Si TFT serial DAC's, which converts serial digital data to an analog signal, could convert one bit within $2.8{\mu}s$. The driver circuits for one data line occupied $8100{\times}50{\mu}m^2$ with $4{\mu}m$ design rule.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.302-307
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• 2005

Recently, lots of parallel mechanisms for spatial 3-DOF and 6-DOF were investigated. However, research on 4-DOF and 5-DOF parallel mechanisms has been very few. In this paper, we propose a 4-DOF parallel mechanism that consists of 3-rotational and 1-translational motions. The kinematic characteristics of this mechanism are analyzed in terms of an isotropic index and maximum force transmission ratio, and its kinematic optimization is being conducted to ensure enhanced kinematic performances

• 대한기계학회논문집A
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• 제21권11호
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• pp.1871-1884
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• 1997

This paper describes the design process of a 3-component load cell with a multiple parallel plate structure which may be used to measure transverse forces and twisting moment simultaneously. Also we have derived equations to predict the bending strains on the surface of the beams in the multiple parallel plate structure under transverse force or twisting moment. It reveals that the bending strains calculated from the derived equations are in good agreement with the results from finite element analysis and experiment. Also we have evaluated the rated output and interference error of each component, which can be efficiently used to design a 3-component load cell with a multiple parallel plate structure.

• 전자공학회논문지SC
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• 제43권6호
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• pp.40-47
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• 2006

본 논문은 CRC 회로의 성능을 향상시키기 위하여 파이프라인 구조를 적용한 병렬 CRC 회로 설계 방법을 제시한다. 입력 데이터의 폭이 CRC 다항식의 차수보다 큰 병렬 CRC 회로를 파이프라인 구조로 변형하기 위하여 로직을 분할하고 파이프라인 단계의 길이를 결정하고, 각 파이프라인 단계에 레지스터를 삽입하는 알고리즘을 제시한다. 여러 가지 타입의 병렬 CRC 회로에 대해, 본 논문에서 제안한 방식이 현저하게 성능을 향상 시켰음을 알 수 있다.

• Journal of Electrical Engineering and Technology
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• 제13권3호
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• pp.1251-1264
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• 2018

The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for $220-V_{rms}/50-Hz$ utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.