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Design of Pipelined Parallel CRC Circuits  

Yi, Hyun-Bean (Dept. of Computer Science & Engineering, Hanyang University)
Kim, Ki-Tae (Dept. of Computer Science & Engineering, Hanyang University)
Kwon, Young-Min (Dept. of Intelligent IT System Research Center, Korea Electronics Technology Institute)
Park, Sung-Ju (Dept. of Electronical Engineering Computer Science, Hanyang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.43, no.6, 2006 , pp. 40-47 More about this Journal
Abstract
This paper introduces an efficient CRC logic partitioning algorithm to design pipelined parallel CRC circuits aimed at improving speed performance. Focusing on the cases that the input data width is greater than the polynomial degree, equations are derived to divide the parallel CRC logic and decide the length of the pipeline stage. Through design experiments on different types of parallel CRC circuits, we have found a significant reduction in delay by adopting our approach.
Keywords
Parallel CRC; pipeline; logic partitioning; logic-level;
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