• Journal of Multimedia Information System
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• v.5 no.3
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• pp.201-208
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• 2018

High Efficiency Video Coding range extensions (HEVC RExt) is a kind of extension model of HEVC. HEVC RExt was specially designed for dealing the high quality images. HEVC RExt is very essential for studio editing which handle the very high quality and various type of images. There are some problems to dealing these massive data in studio editing. One of the most important procedure is re-encoding and decoding procedure during the editing. Various codecs are widely used for studio data editing. But most of the codecs have common problems to dealing the massive data in studio editing. First, the re-encoding and decoding processes are frequently occurred during the studio data editing and it brings enormous time-consuming and video quality loss. This paper, we suggest new video coding structure for the efficient studio video editing. The coding structure which is called "ultra-low delay (ULD)". It has the very simple and low-delayed referencing structure. To simplify the referencing structure, we can minimize the number of the frames which need decoding and re-encoding process. It also prevents the quality degradation caused by the frequent re-encoding. Various fast coding algorithms are also proposed for efficient editing such as tool-level optimization, multi-serve based distributed coding and SIMD (Single instruction, multiple data) based parallel processing. It can reduce the enormous computational complexity during the editing procedure. The proposed method shows 9500 times faster coding speed with negligible loss of quality. The proposed method also shows better coding gain compare to "intra only" structure. We can confirm that the proposed method can solve the existing problems of the studio video editing efficiently.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.17-26
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• 2006

The analog Viterbi decoder for the PR (1 2 2 1) which is used for BVD read channel is designed with circular analog parallel circuits. Since the inter symbol interference is serious problem in the high density magnetic storage device or DVD, the PRML technology is normally employed for the purpose of minimizing the decoding error. The feature of the PRML technology is with the multi-level coding according to the predetermined combining rule among the neighboring symbols and with the decoding according to the known combining rule. Though the conventional PRML technology is implemented with the digital circuits, the recent trend towards this end is with the utilization of the analog circuits due to the requirements of higher speed and lower power in the DVD read channel. In this study, the Viterbi decoder which is the bottleneck of the PRML implementation is designed with the analog parallel circuit structure. The designed Viterbi decoder for the PR (1 2 2 1) signal shows 3 times faster in the speed and 1/3 times less in the power consumption than thoseoftheconventionaldigitalcounterpart.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.2
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• pp.62-67
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• 2001

In the recent mobile communication systems, the performance of Turbo Code using the error correction coding depends on the interleaver influencing the free distance determination and the recursive decoding algorithms that is executed in the turbo decoder. However, performance depends on the interleaver depth that need a large time delay over the reception process. Moreover, Turbo Code has been known as the robust ending method with the confidence over the fading channel. The International Telecommunication Union(ITU) has recently adopted as the standardization of the channel coding over the third generation mobile communications such as IMT-2000. Therefore, in this paper, we proposed of the method to improve the conventional performance with the parallel concatenated 4-New Turbo Decoder using MAP a1gorithm in spite of complexity increasement. In the real-time video and video service over the third generation mobile communications, the performance of the proposed method was analyzed by the reduced decoding delay using the variable decoding method by computer simulation over AWGN and fading channels.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• ETRI Journal
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• v.20 no.1
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• pp.16-27
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• 1998

In this paper, we consider the acquisition performance of an IS-95 reverse link access channel slot as a function of system design parameters such as postdetection integration length and the number of access channel message block repetitons. The uncertainty region of the reverse link spreading codes compared to that of forward link is very small, since the uncertainty region of the reverse link is determined by a cell radius. Thus, the parallel acquisiton technique in the reverse link is more efficient than a serial acquisition technique in terms of implementation and of acquisition time. The parallel acquisition is achieved by a bank of N parallel I/Q noncoherent correlator are analyzed for band-limited noise and the Rayleigh fast fading channel. The detection probability is derived for multiple correct code-phase offsets and multipath fading. The probability of no message error is derived when rake combining, access channel message block combining, and Viterbi decoding are applied. Numerical results provide the acquisition performance for system design parameters such as postdetection integration length and number of access channel message block repetitions in case of a random access on a mobile station.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.575-578
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• 1998

In this paper, we propose a VLSI architecture of Reed-Solomon decoder. Our goal is the development of an architecture featuring parallel and pipelined processing to improve the speed and low power design. To achieve the this goal, we analyze the RS decoding algorithm to be used parallel and pipelined processing efficiently, and modified the Euclid's algorithm arithmetic part to apply the parallel structure in RS decoder. The overall RS decoder are compared to Shao's, and we show the 10% area efficiency than Shao's time domain decoder and three times faster, in addition, we approve the proposed RS decoders with Altera FPGA Flex 10K-50, and Implemeted with LG 0.6{\mu}$ processing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1C
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• pp.1-8
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• 2005

In this paper, we present a novel LDPC code construction called as semi-algebra low density parity check(LDPC) codes which is one kind of deterministic LDPC code based on dual-diagonal sub-matrix. The constructing method results in a class of high rate LDPC codes. Codes in this class have a large girth and good minimum distances. Furthermore, they can be implemented by simple parallel array architecture using cyclic shift register and perform well with the iterative decoding.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.162-164
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• 2010

H.264/AVC(Advanced Video Coding) is a standard for video compression. H.264/AVC provides good video quality at substantially lower bit rates than previous standards. In this papers, we propose the efficient architecture of H.264/AVC decoder using GPGPU. GPGPU can process many of operation in parallel. IQ/IDCT is possible that parallel processing in H.264/AVC decoding algorithm.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.309-313
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• 2009

In this paper, the network performance of a turbo coded optical code division multiple access (CDMA) system with cross-layer, which is between physical and network layers, concept is analyzed and simulated. We consider physical and MAC layers in a cross-layer concept. An intensity-modulated/direct-detection (IM/DD) optical system employing pulse position modulation (PPM) for satellite broadcasting communications is considered. In order to increase the system performance, turbo codes composed of parallel concatenated convolutional codes (PCCCs) is utilized. The network performance is evaluated in terms of bit error probability (BEP). From the simulation results, it is demonstrated that turbo coding offers considerable coding gain with reasonable encoding and decoding complexity. Also, it is confirmed that the performance of such an optical CDMA network can be substantially improved by increasing the interleaver length and the number of iterations in the decoding process. The results of this paper can be applied to implement the satellite broadcasting communications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.1080-1089
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• 1999

The union upper bounds to the bit error probability of maximum likelihood(ML) soft-decoding of parallel concatenated convolutional codes(PCCC) and serially concatenated convolutional codes(SCCC) can be evaluated through the weight enumerating function(WEF). This union upper bounds become the lower bounds of the BER achievable when iterative decoding is used. In this paper, to compute the WEF, an efficient error event search algorithm which is a combination of stack algorithm and bidirectional search algorithm is proposed. By computor simulation, it is shown that the union boounds obtained by using the proposed algorithm become the lower bounds to BER of concatenated convolutional codes with iterative decoding.