• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.409-410
• /
• 2008

This paper presents nonlinear and parallel design for synchronous pipelining in IP-based H.264 decoder implementation. Since H.264 decoder includes the dataflow of feedback loop, the data dependency requires one NOP stage per pipelining latency to drop the throughput into 1/2. Further, it is found that, in execution time, the stage scheduled for MC is more occupied than that for CAVLD/ITQ/DF. The less efficient stage would be improved by nonlinear scheduling, while the fully-utilized stage could be accelerated by parallel scheduling of IP. The optimization yields 3 nonlinear {CAVLD&ITQ}|3 parallel (MC/IP&Rec.)| 3 nonlinear {DF} pipelined architecture for IP-based H.264 decoder. In experiments, the nonlinear and parallel pipelined H.264 decoder, including existing IPs, could deal with full HD video at 41.86MHz, in real time processing.

• 한국산업정보학회논문지
• /
• 제11권5호
• /
• pp.163-169
• /
• 2006

In order to use parallel computers in specific applications, algorithms need to be developed and mapped onto parallel computer architectures. Main memory access for shared memory system or global communication in message passing system deteriorate the computation speed. In this paper, it is found that the m-step generalization of the block Lanczos method enhances parallel properties by forming in simultaneous search direction vector blocks. QR factorization, which lowers the speed on parallel computers, is not necessary in the m-step block Lanczos method. The m-step method has the minimized synchronization points, which resulted in the minimized global communications and main memory access compared to the standard methods.

• 한국정보처리학회논문지
• /
• 제6권3호
• /
• pp.792-803
• /
• 1999

Most data parallel language compilers are source-to-source translators. Most Compilers of HPF which is recognized as a standard data parallel language convert a parallel program in PHF in a Fortran 77 program inserted message passing primitives. By the way, they currently generate significant amount of ineffective codes in the course of the conversion. Especially, FORALL construct is converted into several DO loops, so loop overhead of these codes is very increased. In this paper, we define and use relation distance vector to keep necessary informations. Then we evaluate and analyze execution time for the codes converted by our method and by PARADIGM method for various array sizes.

• Journal of Power Electronics
• /
• 제13권3호
• /
• pp.437-446
• /
• 2013

This paper proposes a design scheme for an LCL-filter used for the three-parallel operation of the power converters in high-capacity wind turbines. The designs of the power devices and grid connected filter are difficult due to the high level voltages and currents in huge-capacity wind turbines. To solve these problem, this paper presents three-parallel operation and LCL-filter design techniques optimized by parallel operation. Furthermore, the design of an inverter side inductance of the LCL-filter is discussed in detail considering the switching modulation method. Simulation and experimental results demonstrate the validity of the designed filter and wind turbines.

• Journal of Power Electronics
• /
• 제5권4호
• /
• pp.312-318
• /
• 2005

This paper presents a compensator for reduction of the reactive lateral current in multiple autonomously controlled uninterruptible power supplies (UPS) connected in parallel. This compensator acts directly on the control equation for voltage amplitude and it provides an improved current distribution especially in the case of parallel connection of UPSs with different output power ratings. Observations show that the original control equation for output voltage amplitude is efficient for voltage regulation but it causes great variation of voltage levels. A compensator with the same structure is added to counterbalance the variation caused by the original control equation. Simulations show promising results with the employment of the proposed compensator. Our simulations are confirmed by experimental results using three UPSs with different output ratings and voltage limiters ($1\%$) connected in parallel under various conditions.

• 한국컴퓨터정보학회논문지
• /
• 제16권5호
• /
• pp.1-11
• /
• 2011

최근 모바일 멀티미디어 기기들의 사용이 증가 하면서 고성능 멀티미디어 프로세서에 대한 필요성이 증가하고 있다. 본 논문에서는 낮은 소비전력으로 고성능 멀티미디어 애플리케이션을 구현할 수 있는 SIMD기반 병렬프로세서를 제안한다. 제안하는 병렬프로세서는 16개의 프로세싱 엘리먼트로 구성되어 있으며, 3단계 파이프라인 구조로 설계되었다. 모의실험 결과, 제안한 SIMD기반 병렬프로세서는 기존의 병렬프로세서보다 프로세싱 엘리먼트 당 상대 연산 처리량에서 높은 성능을 보였으며, 또한 동일한 130nm 테크놀리지와 720 클록주파수에서 상용 고성능 프로세서인 TI C6416보다 1.4~31.4배의 성능 향상 및 5.9~8.1배의 에너지 효율 향상을 보였다. 제안한 병렬프로세서를 하드웨어 설계언어인 verilog HDL을 이용하여 설계하였고, FPGA를 이용해 검증하였다.

• 설비공학논문집
• /
• 제10권2호
• /
• pp.202-216
• /
• 1998

A computer simulation for the performance analysis of automobile air conditioning components is carried out for the various operating conditions. The automobile air conditioning system consists of laminated type evaporator, swash plate type compressor, parallel flow type condenser, externally equalized thermostatic expansion valve and receiver drier. The overall heat transfer coefficient and the pressure drop in laminated type evaporator were obtained through experiments. In parallel flow type condenser, the performance analysis computer program using the empirical equation for heat transfer coefficient has been developed and the results are compared with experimental results. A model for matching the performance analysis programs of respective components .of automobile air conditioning system is introduced. Further, the effects of varying condenser size and refrigerant charge on the performance of automobile air conditioning system are discussed clearly.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권3호
• /
• pp.345-355
• /
• 2014

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
• /
• pp.152-154
• /
• 2004

In 2004, Ku-Chen proposed an improvement to Chien et al.'s scheme to prevent from some weaknesses. Lee et al. also proposed an improvement to Chien et al.'s scheme to prevent from parallel session attack. This paper, however, will demonstrate that Ku-Chen's scheme is still vulnerable to the parallel session attack and Lee et al.'s scheme is also vulnerable to masquerading server attack.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 ITC-CSCC -1
• /
• pp.333-336
• /
• 2000

We discuss the direct methods (Gauss-Jordan and Gaussian eliminations) to solve linear systems on distributed memory parallel computers. It will be shown that the so-called row-cyclic storage gives rise to the best performance among the standard three (row-cyclic, column-cyclic and cyclic-cyclic) data storages. We also show that Gauss-Jordan elimination, rather than Gaussian elimination, is highly efficient for the direct solution of linear systems in parallel processing, though Gauss-Jordan elimination requires a larger number of arithmetic operations than Gaussian elimination. Numerical experiment is performed on HITACHI SR12201 with the standard libraries MPI and BLAS.