• Title/Summary/Keyword: Paper circuit computing

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Design of inversion and division circuit over GF($2^{m}$) (유한체 $GF(2^{m})$상의 역원계산 회로 및 나눗셈 회로 설계)

  • 조용석;박상규
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.5
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    • pp.1160-1164
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    • 1998
  • In this paper, we propose a new algorithm for computing multiplicative inverses in $GF(2^{m})$ and design an inversion circuit and a division circuit using this algorithm. The algorithm used is based on Fermat's theorem. It takes around m/2 clock cycles. The hardware requirements of the inversion circuit and the division circuit using this algorithm are the same as traditional circuits except for the addition of multiplexers.

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SoftMax Computation in CNN Using Input Maximum Value (CNN에서 입력 최댓값을 이용한 SoftMax 연산 기법)

  • Kang, Hyeong-Ju
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.2
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    • pp.325-328
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    • 2022
  • A convolutional neural network(CNN) is widely used in the computer vision tasks, but its computing power requirement needs a design of a special circuit. Most of the computations in a CNN can be implemented efficiently in a digital circuit, but the SoftMax layer has operations unsuitable for circuit implementation, which are exponential and logarithmic functions. This paper proposes a new method to integrate the exponential and logarithmic tables of the conventional circuits into a single table. The proposed structure accesses a look-up table (LUT) only with a few maximum values, and the LUT has the result value directly. Our proposed method significantly reduces the space complexity of the SoftMax layer circuit implementation. But our resulting circuit is comparable to the original baseline with small degradation in precision.

Trends in Chip Fabrication Infrastructure for Implementation in Quantum Technology (양자 기술 구현을 위한 칩 제작 인프라 기술 동향)

  • J.W. Kim;K.W. Moon;J.J. Ju
    • Electronics and Telecommunications Trends
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    • v.38 no.1
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    • pp.9-16
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    • 2023
  • In the rapidly growing field of quantum computing, it is evident that a robust supply chain is needed for commercialization or large-scale production of quantum chips. As a result, the success of many R&D projects worldwide relies on the development of quantum chip foundries. In this paper, a variety of quantum chip foundries, particularly the ones creating photonic integrated circuit (PIC) quantum chips, are reviewed and summarized to demonstrate current technological trends. Global projects aiming to establish new foundries, as well as information regarding their respective funding, are also included to identify the evolutionary direction of quantum computing infrastructure. Furthermore, the potential application of lithium niobate as a novel material platform for quantum chips is also discussed.

Design of Reliable Adaptive Fitter with Fault Tolerance Using DSP (DSP를 이용한 고장허용을 갖는 신뢰 적응 필터 설계)

  • 유동완;이전우;서보혁
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.50 no.1
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    • pp.8-13
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    • 2001
  • LMS algorithm has been used for plant identifier and noise cancellation. This algorithm has been researched for performance enhancement of filtering. The design and development of a reliable system has been becoming a key issue in industry field because the reliability of a system is considered as an important factor to perform the system's function successfully. And the computing with reliability and fault tolerance is a important factor in the case of aviation, system communication, and nuclear plant. This paper presents design of reliable adaptive filter with fault tolerance. Generally, redundancy is used for reliability. In this case it needs computing or circuit for voting mechanism, or fault detection. Therefore it has simple computing, and practicality for application. And in this paper, reliability of adaptive filter is analyzed. The effectiveness of the proposed adaptive filter is demonstrated to the case studies of plant identifier and noise cancellation by using DSP.

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Realization of Multiple-Control Toffoli gate based on Mutiple-Valued Quantum Logic (다치양자논리에 의한 다중제어 Toffoli 게이트의 실현)

  • Park, Dong-Young
    • Journal of Advanced Navigation Technology
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    • v.16 no.1
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    • pp.62-69
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    • 2012
  • Multiple-control Toffoli(MCT) gates are macro-level multiple-valued gates needing quantum technology dependent primitive gates, and have been used in Galois Field sum-of-product (GFSOP) based synthesis of quantum logic circuit. Reversible logic is very important in quantum computing for low-power circuit design. This paper presents a reversible GF4 multiplier at first, and GF4 multiplier based quaternary MCT gate realization is also proposed. In the comparisons of MCT gate realization, we show the proposed MCT gate can reduce considerably primitive gates and delays in contrast to the composite one of the smaller MCT gates in proportion to the multiple-control input increase.

Design of Reliable Adaptive Filter with Fault Tolerance Using TMS320C32 (TMS320C32를 이용한 고장허용을 갖는 신뢰 적응 필터 설계)

  • Ryoo, Dong-Wan;Seo, Bo-Hyeok
    • Proceedings of the KIEE Conference
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    • 2000.07d
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    • pp.2429-2432
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    • 2000
  • Adaptive filter algorithm has been used for plant identifier and noise cancellation. This algorithm has been researched for performance enhancement of filtering. The design and development of a reliable system has been becoming a key issue in industry field because the reliability of a system is considered as an important factor to perform the system's function successfully. And the computing with reliability and fault tolerance is a important factor in the case of aviation and nuclear plant. This paper presents design of reliable adaptive filter with fault tolerance. Generally, redundancy is used for reliability. In this case it needs computing or circuit for voting mechanism or computing for fault detection or switching part. But this presented Filter is not in need of computing for voting mechanism, or fault detection. Therefore it has simple computing, and practicality for application. And in this paper, reliability of adaptive filter is analyzed. The effectiveness of the proposed adaptive filter is demonstrated to the case studies of plant identifier and noise cancellation by using DSP.

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An Optimum Architecture for Implementing SEED Cipher Algorithm with Efficiency (효율적인 SEED 암호알고리즘 구현을 위한 최적화 회로구조)

  • Shin Kwang-Cheul;Lee Haeng-Woo
    • Journal of Internet Computing and Services
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    • v.7 no.1
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    • pp.49-57
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    • 2006
  • This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 12B-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array, This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We have designed the circuit with the VHDL coding, implemented with a FPGA of 50,000 gates.

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Design Optimization of the Arithmatic Logic Unit Circuit for the Processor to Determine the Number of Errors in the Reed Solomon Decoder (리드솔로몬 복호기에서 오류갯수를 계산하는 처리기의 산술논리연산장치 회로 최적화설계)

  • An, Hyeong-Keon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.11C
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    • pp.649-654
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    • 2011
  • In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

An Non-Scan DFT Scheme for RTL Circuit Datapath (RTL 회로의 데이터패스를 위한 비주사 DFT 기법)

  • Chang, Hoon;Yang, Sun-Woong;Park, Jae-Heung;Kim, Moon-Joon;Shim, Jae-Hun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.2
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    • pp.55-65
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    • 2004
  • In this paper, An efficient non-scan DFT method for datapaths described in RTL is proposed. The proposed non-scan DFT method improves testability of datapaths based on hierarchical testability analysis regardless to width of the datapath. It always guarantees higher fault efficiency and faster test pattern generation time with little hardware overhead than previous methods. The experimental result shows the superiority of the proposed method of test pattern generation time, application time, and area overhead compared to the scan method.

User interface of Home-Automation for the physically handicapped Person in wearable computing environment (웨어러블 환경에서의 수족사용 불능자를 위한 홈오토메이션 사용자 인터페이스)

  • Kang, Sun-Kyung;Kim, Young-Un;Han, Dae-Kyung;Jung, Sung-Tae
    • Journal of the Korea Society of Computer and Information
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    • v.13 no.5
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    • pp.187-193
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    • 2008
  • Interface technologies for a user to control home automation system in wearable computing environment has been studied recently. This paper proposes a new interface method for a disabled person to control home automation system in wearable computing environment by using EOG sensing circuit and marker recognition. In the proposed interface method, the operations of a home network device are represented with human readable markers and displayed around the device. A user wearing a HMD, a video camera, and a computer selects the desired operation by seeing the markers and selecting one of them with eye movement from the HMD display The requested operation is executed by sending the control command for the selected marker to the home network control device. By using the EOG sensing circuit and the marker recognition system a user having problem with moving hands and fit can manipulate a home automation system with only eye movement.

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