• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.33-33
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• 2007

SoP-L 공정은 유전율이 상이한 재료를 이용하여 PCB 공정이 가능하고 다른 packaging 방법에 비해 공정 시간과 비용이 절약되는 잠정이 있다. 본 연구에서는 SoP-L 기술을 이용하여 Si 기판의 함몰에 판한 공정의 안정도와 함몰 시 제작된 때턴의 특성의 변화에 대해 관찰 하였다. Si 기판의 함몰에 Active device를 이용하여 특성의 변화를 살펴보고 공정의 안정도를 확립하려 했지만 Active device는 측정 시 bias의 확보와 특성의 민감한 변화로 인해 비교적 측정이 용이하고 공정의 test 지표를 삼기 위해 passive device 를 구현하여 함몰해 보았다. Passive device 의 제작 과정은 Si 기판 위에 spin coating을 통해 PI(Poly Imide)를 10um로 적층한 후에 Cr과 Au를 seed layer로 증착을 하였다. 그리고 photo lithography 공정을 통하여 photo resister patterning 후에 전해 Cu 도금을 거쳐 CPW 구조로 $50{\Omega}$ line 과 inductor를 형성하였다. 제작 된 passive device의 함몰 전 특성 추출 data와 SoP-L공정을 통한 함몰 후 추출 data 비교를 통해 특성의 변화와 공정의 안정도를 확립하였다. 차후 안정된 SoP-L 공정을 이용하여 Active device를 함몰 한다면 특성의 변화 없이 size 룰 줄이는 효과와 외부 자극에 신뢰도가 강한 기판이 제작 될 것으로 예상된다.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1929_1930
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• 2009

Fully embedded tunable bandpass filter (BPF) with inductive coupling circuits is newly designed and demonstrated for UHF TV tuner ranged from 500MHz to 900MHz receivers. Conventional RF tuning circuit with an electromagnetic coupled tunable filter has several problems such as large size, high volume, and high cost, since the electromagnetic coupled filter is comprised of several passive components and air core inductors to be assembled and controlled manually. To address these obstacles, compact tunable filter with inductive coupling circuit was embedded into low cost organic package substrate. The embedded filter was optimally designed to have high performance by using high Q spiral stacked inductors, high dielectric $BaTiO_3$ composite MIM capacitors, varactor diodes. It exhibited low insertion loss of approximately -2dB, high return loss of below -10dB, and large tuning range of 56.3%. It has an extremely compact size of $3.4{\times}4.4{\times}0.5mm^3$.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.323-323
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• 2013

High power light-emitting diodes (LEDs) are widely used in many device applications due to its ability to operate at high power and produce high luminance. However, releasing the heat accumulated in the device during operating time is a serious problem that needs to be resolved to ensure high optical efficiency. Ceramic or Aluminium base metal printed circuit boards are generally used as integral parts of communication and power devices due to its outstanding thermal dissipation capabilities as heat sink or heat spreader. We investigated the characterisation of electroless plating of Ni-B film according to plating bath temperature, ranging from $50^{\circ}C$ to $75^{\circ}C$ on Ag paste/anodised Al ($Al_2O_3$)/Al substrate to be used in metal PCB for high power LED packing systems. X-ray diffraction (XRD), Field-Emission Scanning Electron Microscopy (FE-SEM) and X-ray Photoelectron Spectroscopy (XPS) were used in the film analysis. By XRD result, the structure of the as deposited Ni-B film was amorphous irrespective of bath temperature. The activation energy of electroless Ni-B plating was 59.78 kJ/mol at the temperature region of $50{\sim}75^{\circ}C$. In addition, the Ni-B film grew selectively on the patterned Ag paste surface.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.96-99
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• 2000

We presents a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and examined electrical parameters with a HP5475A TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3 $\times$ 3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, self inductance 146pH, mutual capacitance 10.9fF and mutual inductance 16.9pH. S parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55㎓ and the loss of 0.26dB. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

• ETRI Journal
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• v.35 no.4
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• pp.625-631
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• 2013

For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.47-53
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• 2015

The effects of electroless nickel immersion gold (ENIG) and organic solderability preservative (OSP) surface finishes on the in-situ intermetallics reaction and the electromigration (EM) reliability of Sn-3.0Ag-0.5Cu (SAC305) solder bump were systematically investigated. After as-bonded, $(Cu,Ni)_6Sn_5$ intermetallic compound (IMC) was formed at the interface of the ENIG surface finish at solder top side, while at the OSP surface finish at solder bottom side,$ Cu_6Sn_5$ and $Cu_3Sn$ IMCs were formed. Mean time to failure on SAC305 solder bump at $130^{\circ}C$ with a current density of $5.0{\times}10^3A/cm^2$ was 78.7 hrs. EM open failure was observed at bottom OSP surface finish by fast consumption of Cu atoms when electrons flow from bottom Cu substrate to solder. In-situ scanning electron microscope analysis showed that IMC growth rate of ENIG surface finish was much lower than that of the OSP surface finish. Therefore, EM reliability of ENIG surface finish was higher than that of OSP surface finish due to its superior barrier stability to IMC reaction.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.23-29
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• 2006

Ultrasonic soldering of Si-wafer to FR-4 PCB at ambient temperature was investigated. The UBM of Si-substrate was Cu/ Ni/ Al from top to bottom with thickness of $0.4{\mu}m,\;0.4{\mu}m$, and $0.3{\mu}m$ respectively. The pad on FR-4 PCB comprised of Au/ Ni/ Cu from top to bottom with thickness of $0.05{\mu}m,\;5{\mu}m$, and $18{\mu}m$ respectively. Sn-3.5wt%Ag foil rolled to $100{\mu}m$ was used for solder. The ultrasonic soldering time was varied from 0.5 s to 3.0 s and the ultrasonic power was 1,400 W. The experimental results show that a reliable bond by ultrasonic soldering at ambient temperature was obtained. The shear strength increased with soldering time up to a maximum of 65 N at 2.5 s. The strength decreased to 34 N at 3.0 s because cracks were generated along the intermetallic compound between Si-wafer and Sn-3.5wt%Ag solder. The Intermetallic compound produced by ultrasonic soldering between the Si-wafer and the solder was $(Cu,Ni)_{6}Sn_{5}$.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.7 no.3
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• pp.17-25
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• 2012

Wire bonding process in making semiconductor needs the most precise control and Critical To Quality(CTQ). Thus, it is regarded to be the most essential step in packaging process. In this process, pure gold wire is used to connect the chip and PCB(substrate or lead frame). However, the price of gold has been skyrocketing continuously for a long period of time and is expected to further increase in the near future. This phenomenon situates us in an unfavorable condition amidst the competitive environment. To avoid this situation, many semiconductor material making companies developed new types of wires: Au.Ag wire is one material followed by many others. This study is aimed to optimize the parameter in wire bonding with the use of 6sigma and QFD(Quality Function Deployment). 6sigma process is a good means to not only solve the problem, but to increase productivity. In order to find the key factor, we focused on VOB(Voice of Business) and VOC(Voice of Customer). The main factors from VOB, VOC are called CTQ. However, there were times when these main factors were far from offering us the correct answer, thus making the situation more difficult to handle. This study shows that QFD aids in deciding which of the accurate factors to undertake. Normally QFD is used in designing and developing products. 6sigma process is held more effective when it used with QFD.