• Transactions of the Korean Society of Mechanical Engineers A
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• v.21 no.6
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• pp.951-960
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• 1997

Package crack caused by the soldering process in the surface mounting plastic package is evaluated by applying the maximum energy release rate criterion. It could be shown that the crack propagation from the lower edge of the ie pad is easily occurred at the maximum temperature during the soldering process, where the pressure acting on the crack surface is assumed by the saturated vapor pressure at maximum temperature. The package crack formation depends on various parameters such as chip size, relative thickness, material properties, the moisture content and soldering temperature etc. The quantitative measure of the effects of the parameters could be easily obtained by using the taguchi's method which requires only a few kinds of combinations with such parameters. From the results, it could be obtained that the more significant parameters to effect the package reliability are the orders of Young's modulus, die pad size, down set, chip thickness and maximum soldering temperature.

• Journal of the Korean Society of Industry Convergence
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• v.2 no.2
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• pp.131-137
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• 1999

Package crack caused by the soldering process in the surface mounting plastic package is evaluated by applying the energy release rate criterion. The package crack formation depend on various parameters such as chip set, chip size, package thickness, package width, material properties and the moisture content etc. The effects of chip set and the other parameters were estimated during the analysis of package cracks which were located in the edge of the upper interface of the chip and the lower interlace of the die pad. From the results, it could be obtained that the more significant parameters to effect the chip set are chip width.

• Tribology and Lubricants
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• v.21 no.2
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• pp.71-76
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• 2005

This paper compares of mechanical tensile properties of 6 kinds of copper foil. The beam lead made with copper foil. Different from other package type such as plastic package, Chip Size Package has a reliability problem in beam lead rather than solder joint in board level. A new tensile loading system was developed using voice-coil actuator. The new tensile loading system has a load cell with maximum capacity of 20 N and a non-contact position measuring system based on the principle of capacitance micrometry with 0.1nm resolution for displacement measurement. Strain was calculated from the measured displacement using FE analysis. The comparison of mechanical properties helps designer of package to choose copper for ensuring reliability of beam lead in early stage of semiconductor development.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.1
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• pp.1-6
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• 2022

The mobile device industry demands much higher levels of integration and lower costs coupled with a growing awareness of the complete system's configuration. A subsystem module package is similar to a board-level circuit that integrates a system function in a package beyond a System-in-Package (SiP) design. It is an advanced IC packaging solution to enhance the PDN and achieve a smaller form factor. Unlike a system-level design with a decoupling capacitor, a subsystem module package system needs to redefine the role of the capacitor and its configuration for PDN performance. Specifically, the design of package's form factor should include careful consideration of optimal PDN performance and the number of components, which need to define the decoupling capacitor's value and the placement strategy for a low impedance profile with associated cost benefits. This paper will focus on both the static case that addresses the voltage (IR) drop and AC analysis in the frequency domain with three specific topics. First, it will highlight the role of simulation in the subsystem module design for the PDN. Second, it will compare the performance of double-sided component placement (DSCP) motherboards with the subsystem module package and then prove the advantage of the subsystem module package. Finally, it will introduce three-terminal decoupling capacitor (decap) configurations of capacitor size, count and value for the subsystem module package to determine the optimum performance and package density based on the cost-effective model.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.45-49
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• 2022

Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.

• International Journal of Quality Innovation
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• v.8 no.3
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• pp.81-112
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• 2007

In the competitive global market, firms have to keep profit from innovation activities. A firm makes profits by offering products or services at a lower cost than its competitors or by offering differentiated products at premium prices that more than compensate for the extra cost of differentiation. The IC Package and Testing technology industries were the first high technological industry to build in Taiwan. The Package and Testing industries in Taiwan adopted competitive innovation activities to become stronger. In our study, we want to know how innovation activities influence a firm operating in the IC Package and Testing industries. Our study used a questionnaire and Likert five-point scale to survey the innovation activities, customer and feedback in innovation performance in the IC Package and Testing industry. The wafer level chip size packing technology in our study indicates the innovation activities. Because we need to compare the difference between the wafer level chip size packing technology and wire bonding technology to recognize innovation and how the innovator and customer were influenced. Our conclusions are described below: (1) When the innovator adopts innovation activities that can be maintained using experiments and knowledge, using machine and decision variables more quickly will produce success; (2) Innovators should adopt innovation activities that focus on customers that use knowledge and experimentation, training time and cost. If an innovation forces customers to spend much time and cost to learn new technology or applications, the innovation will not be adopted; (3) Innovators that create innovation performance higher than his customers must also consider the impact upon their customers. We have to remind innovator to focus on why their customers have a different level of evolution in the same innovation activities.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.127-154
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• 1999

Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

• Proceedings of the KSME Conference
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• 2000.11a
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• pp.607-611
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• 2000

Acoustic modal property of the vehicle passenger compartment is a very important factor which dominates vehicle interior noise in the low frequency range. In most real cars, trunk noise often transfers into the passenger compartment since the two cavities are acoustically coupled. This study identifies the major coupling path by examining the variation of the coupled acoustic modal frequencies and modes. An 1/2 size acryl compartment model is designed and manufactured for the measurement and analysis of coupled acoustic modes. Experimental result shows that package tray contributes to the coupling much more than the back seat and hole size of the package tray is an important design factor to control low frequency acoustic modes in the coupled system.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.6
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• pp.201-204
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• 2007

In this paper, fully embedded and miniaturized diplexer device has been developed and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into a low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23 dB at 824-894 MHz and -0.7 and -22 dB at 1850-1990 MHz, respectively. Its size is $3.9mm{\times}3.9mm{\times}0.77mm$. The fabricated diplexer is the smallest one which is fully embedded into a low cost organic package substrate.