• Transactions on Electrical and Electronic Materials
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• 제18권2호
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• pp.59-61
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• 2017

This research was analyzed thermal characteristics that was appointed disadvantage when smart LED driver ICs was packaged and we applied extracted thermal characteristics for optimal layout design. We confirmed reliability of smart LED driver ICs package without additional heat sink. If the package is not heat sink, we are possible to minimize package. For extracting thermal loss due to overshoot current, we increased driver current by two and three times. As a result of experiment, we obtained 22 mW and 49.5 mW thermal loss. And we obtained optimal data of 350 mA driver current. It is important to distance between power MOSFET and driver ICs. If the distance was increased, the temperature of package was decreased. And so we obtained optimal data of 3.7 mm distance between power MOSFET and driver ICs. Finally, we fabricated real package and we analyzed the electrical characteristics. We obtained constant 35 V output voltage and 80% efficiency.

• 한국인쇄학회지
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• 제30권2호
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• pp.47-58
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• 2012

The purpose of this study is to provide how various elements of package design affect on consumer response. Those consumers who is living at Sung-nam district and who is using or have used herbal shampoo were selected as respondents for this research. For testing hypotheses. frequency analysis, reliability analysis, and multi regression analysis were utilized with SPSS 12. All elements of package design influenced on brand attitude and purchasing intention. Typography is the most effective element influencing on brand attitude, while illustration is on purchasing intention. This result could be a useful reference for package designer and brand manager to trigger positive brand attitude and purchasing intention.

• 대한인간공학회지
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• 제30권5호
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• pp.659-669
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• 2011

Objective: The aim of this study is to suggest a package layout guideline for low-floor bus by interview with passengers and observations of their behavior. Background: Increasing attention has been introduced the low-floor bus to be more suitable for use by transportation handicapped. Complex issues are involved in providing comfortable services to all people. We are going to suggest package layout guidelines for more comfortable and suitable travel to all people. Method: The two times of survey and video observation sessions were conducted on low-floor buses in Seoul; (1) a finding of potential issues in the first session, (2) a confirming of issues from the last session. Results: The three of major issues were founded in this study; (1) difficulties in supporting body when standing, (2) difficulties in sitting on front wheel pan seat, (3) difficulties in passing through the aisle. Conclusion: There were clear differences between public and transportation handicapped in using some tools which are used for support body such as roof hand rails, side hand rails, and hand rail rings. Some of design problems were founded to improve from the perspective of ergonomics and universal design. Such differences and design guidelines have to be considered in bus design as well as commercial vehicle. Application: The proposed design guidelines can be used to development of low-floor bus and other public transportations.

• 마이크로전자및패키징학회지
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• 제13권4호
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• pp.1-7
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• 2006

WLCSP(wafer level chip size package)는 웨이퍼 레벨에서 패키지 공정이 이루어지는 차세대 패키지 중 하나이다. WLCSP는 웨이퍼 레벨에서 패키지 공정이 이루어진다는 특징으로 인하여 웨이퍼당 생산되는 반도체 칩의 수에 따라 그 패키징 비용을 크게 줄일 수 있다는 장점이 있다. 그러나 응력 버퍼 역할을 하는 기판을 없애는 혁신적인 구조로 인하여 솔더 조인트의 신뢰성이 기존의 BGA 패키지에 비하여 취약하게 되는데, 이러한 솔더 조인트 신뢰성에 대하여 반도체 칩과 솔더볼을 연결하는 폴리머 절연층은 열팽창계수 차이에 의해 발생하는 응력을 흡수하는 중요한 역할을 하게 된다. 본 연구에서는 하이닉스에서 개발한 Omega-CSP를 사용하여 솔더볼 배열 변화와 제 1 절연층의 특성에 따른 솔더 조인트의 열피로 특성을 평가하였다. 그 결과 절연층의 특성 변화가 솔더 조인트의 열피로 특성에 주는 영향은 솔더볼 배열 구조에 따라 변화되는 것을 확인하였다.

• 한국전기전자재료학회논문지
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• 제29권3호
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• pp.131-134
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• 2016

This research was analyzed thermal characteristics that was appointed disadvantage when smart LED driver ICs was packaged and we applied extracted thermal characteristics for optimal layout design. We confirmed reliability of smart LED driver ICs package without additional heat sink. If the package is not heat sink, we are possible to minimize package. For extracting thermal loss due to overshoot current, we increased driver current by two and three times. As a result of experiment, we obtained 22 mW and 49.5 mW thermal loss. And we obtained optimal data of 350 mA driver current. It is important to distance between power MOSFET and driver ICs. If thhe distance was increased, the temperature of package was decreased. And so we obtained optimal data of 3.7 mm distance between power MOSFET and driver ICs. Finally, we fabricated real package and we analyzed the electrical characteristics. We obtained constant 35 V output voltage and 80% efficiency.

• Communications for Statistical Applications and Methods
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• 제28권4호
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• pp.369-391
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• 2021

The vlda is an R (R Development Core team et al., 2011) package which provides functions for visualization of multidimensional longitudinal data. In particular, the R package vlda was developed to assist in producing a plot that more effectively expresses changes over time for two different types (long format and wide format) and uses a consistent calling scheme for longitudinal data. The main features of this package allow us to identify the relationship between categories and objects using an indicator matrix with object information, as well as to cluster objects. The R package vlda can be used to understand trends in observations over time in addition to identifying relative relationships at a simple visualization level. It also offers a new interactive implementation to perform additional interpretation, therefore it is useful for longitudinal data visual analysis. Due to the synergistic relationship between the existing VLDA plot and interactive features, the user is empowered by a refined observe the visual aspects of the VLDA plot layout. Furthermore, it allows the projection of supplementary information (supplementary objects and variables) that often occurs in longitudinal data of graphs. In this study, practical examples are provided to highlight the implemented methods of real applications.

• 전자공학회논문지
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• 제49권9호
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• pp.259-269
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• 2012

전원 전압이 낮아지고, 칩의 동작 속도가 빨라짐에 따라 온-칩 인덕턴스를 포함한 power distribution network (PDN) 분석이 중요해 질 것으로 예측된다. 본 논문에서는 일반적인 온-칩 전력 격자 구조에 적용시킬 수 있는 효과적인 인덕턴스 추출방법에 대해 제안한다. Chip layout에 적용할 수 있는 loop 인덕턴스 모델을 제시하고, 그 모델을 사용하여 post layout RC extraction netlist로 부터 인덕턴스를 포함한 netlist를 추출할 수 있는 tool을 개발하였다. 제안된 loop 인덕턴스 모델과 개발된 tool의 정확성은 회로 simulation을 통해 PEEC 모델과 비교하여 검증하였다. 인덕턴스 추출 방법을 실제 chip layout에 적용시켜 on-chip inductance를 포함한 PDN의 voltage fluctuation을 예측하였다. 패키지와 PCB 모델을 포함한 co-simulation 모델을 구성하여 on-chip inductance의 영향을 분석하였다.

• 정보처리학회논문지B
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• 제9B권2호
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• pp.245-254
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• 2002

머신비전을 이용한 IC 패키지 마킹검사 시스템은 입력영상으로부터 검사할 요소들의 위치를 식별하고, 추출된 요소들을 학습된 표준 패턴과 비교하여 마킹의 불량 여부를 판단한다. 본 논문에서는 검사 대상 IC 패키지의 위치 판별, 마킹문자 추출, 핀원딤플 검출과 같은 일련의 작업들에 적합한 적응적 다단계 이진화 방법과 마킹문자의 국소적인 오류검출은 물론 잡영에 강건한 정합단위의 동적 선택 방법을 제안한다. 제안하는 이진화 방법은 이진화 대상 영역과 명도 값의 범위를 제한하여 Otsu의 이진화 알고리즘을 적용함으로써 특정 응용에 적응적인 이진화가 가능하다. 정합단위의 동적 선택 방법은 문자추출 및 배치분석에 대한 결과에 따라 정합단위를 선택한다. 그러므로 문자추출 및 배치분석 과정에서 발생하는 예기치 못한 부적절한 상황에서도 가능한 범위내에서 최소의 정합단위를 선택할 수 있다. 제안된 방법을 구현하여 8종의 IC 패키지, 총 280개의 영상에 대하여 실험한 결과, IC 패키지와 핀원딤플의 검출율은 100%였으며, 마킹상태에 대한 판정은 98.8%의 정확도를 나타내어 제안된 방법이 효과적임을 확인할 수 있었다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.890-894
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• 2003

This paper discuss basic functional construction and plant layout of a ELV dismantling system that can maximize the reusability of tarts and the recoverability of materials by dismantling ELV rationally and efficiently. "Island" type was selected for the system configuration considering processing amount, economical efficiency, and effectiveness. The system is supported by the information system, and composed of dismantling stations and handling equipments. The layout of the stations was determined after simulation and optimization using commercial software package, Arena and OptQuest. The objective of the optimization was maximum profit while the system capacity is considered as constraint. The environmental load of ELV can be minimized when the composition and function of each station are embodied in detail and the system is interfaced with shredding operation.

• 제어로봇시스템학회논문지
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• 제5권7호
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• pp.848-854
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• 1999

In this paper, we designed and implemented a precise pulse motor controller chip that generates the pulse needed to control step motor, DC servo and AC servo motors. This chip generates maximum pulse output rate of 5Mpps and has the quasi-S driving capability and speed and moving distance override capability during driving. We designed this chip with VHDL and executed a logic simulation and synthesis using Synopsys tool. The pre-layout simulation and post-layout simulation was executed by Compass tool. This chip was produced with 100 pins, PQFP package by 0.8${\mu}{\textrm}{m}$ gate array process and implemented by completely digital logic. We developed the test hardware board of performance and the CAMC(Computer Aided Motor Controller) Agent softwate to test the performance of the pulse motor controller chip produced. CAMC Agent enables user to set parameters needed to control motor with easy GUI(Graphic User Interface) environment and to display the output response of motor graphically.