• Journal of Power Electronics
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• v.9 no.1
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• pp.124-131
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• 2009

This paper presents a PWM dc-ac converter regulation using a Single Input Fuzzy PI Controller (SIFPIC). The SIFPIC is derived from the signed distanced method, which is a simplification of a conventional fuzzy controller. The simplification results in a one-dimensional rule table, that allows its control surface to be approximated by a piecewise linear relationship. The controller multi-loop structure is comprised of an outer voltage and an inner current feedback loop. To verify the performance of the SIFPIC, a low power PWM dc-ac converter prototype is constructed and the proposed control algorithm is implemented. The experimental results show that the SIFPIC performance is comparable to a conventional Fuzzy PI controller, but with a much reduced computation time.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.4
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• pp.90-99
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• 1998

The DC/DC power converter increase switching frequency in order to achieve small size, a low noise, and light weight. However, the power switches have high power losses and switching stresses as the switching frequency is increased. Therefore in this paper, the author propose the Soft-Switching Forward-Flyback PWM DC/DC converter using assistant-circuit, based on forward-flyback operation of a high-frequency transformer. The proposed converter scheme is verified by simulation and experiment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.493-500
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• 2015

A flyback converter operates with either pulse width modulation (PWM) or pulse frequency modulation (PFM) control scheme depending on the load current. At light load condition, PFM control is employed to reduce the switching frequency and thereby minimize the switching power loss. For heavier load, PWM control is used to regulate the output voltage of the flyback converter. The flyback controller has been implemented in a $0.35{\mu}m$ BCDMOS process and applied to a 40-W flyback converter. The light-load power efficiency of the flyback converter is improved up to 5.7-% comparing with the one operating with a fixed switching frequency.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.50 no.6
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• pp.293-299
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• 2001

This paper proposes a new power conditioning system for the SMES composed of a thyristor PWM converter with a resonant commutation circuit. The operation of the proposed system and the dynamic interaction between SMES and the power system is analyzed by a theoretical approach with equivalent circuits and verified by computer simulations with EMTP, considering a typical 154kV power system. The proposed system can provide a solution for the power factor regulation and harmonic level reduction in the ac terminal with low-cost system configuration.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.8
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• pp.529-535
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• 2000

In this paper, a current control system of a single phase PWM AC/DC converter using a reduced-order Luenberger observer without source voltage sensors is proposed. The sinusoidal input current and unity input power factor are realised based on the estimated source voltage performed by the reduced-order Luenberger observer using actual currents and DC link voltage. The poles of the reduced-order Luenberger observer are placed in the left half plane of s-plane by the pole-placement method in order to acquire the stability of the observer. The magnitude and the phase of the estimated source voltage are used to accomplish the unity power factor. The proposed method is implemented by DSP(Digital Signal Processor). Experimental Results verify that the reduced-order observer estimates the source voltage without the estimation error and the control system accomplishes the unity power factor, and constant DC link voltage.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.622-625
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• 1999

This paper introduces a novel zero-voltage switching (ZVS)) pulse width modulation (PWM) active clamping dc-to-dc boost converter. This technique presents ZVS commutation without additional voltage stress and a significant increase in the circulating reactive energy throughout the converter. Therefore, all of the losses for the switches are minimized, and high power density system can be realized. The characteristics are verified through simulation and experimental results.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1230-1232
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• 2000

To reduce harmonics in the AC line and achieve a unit power factor, A 4 paralled single phase PWM AC/DC converter has been proposed. In this paper, the coupling components are derived analytically from PWM converter input transformer model and control scheme to solve this problem is proposed. Unit power factor was obtained and the AC-side current harmonics were reduced. Simulation results show the usefulness of the proposed method and applicability to PWM converter in auxiliary block of high speed train.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.5
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• pp.490-498
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• 2002

In this paper, a design method of LCL filter at the AC input side of a voltage source PWM converter is proposed. Effective method to prevent pollution of the utility caused by high frequency current ripple is to use a AC input LCL filter, The C elements in the filter provide a low impedance path for the high frequency component, preventing them from entering the utility. The resistors In series with the capacitors are used for damping the resonance in the filter The design examples are shown and the validity of the proposed design method is verified through the PSIM simulation.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.171-175
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• 1998

This paper proposes the advanced PWM method that can reduce common-mode voltage in three-phase PWM converter-inverter system. By the proper distribution of the zero-voltage vector of inverter, it is possible to cancel out a common-mode voltage pulse in a sampling period. Since the proposed PWM method maintains the effective-voltage vector, it does not affect the control performance of converter-inverter system. Without any extra hardware, overall common-mode voltage can be decreased by one-third compared with conventional PWM scheme.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.