• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.495-497
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• 1994

Given the constraint of the AC input power factor and the DC-link voltage and current ripple in voltage source inverter, minimizing the size and cost of the DC-link fitter components is very important. This paper presents a procedure for the selection of DC-link filler element values in a three-phase PWM voltage source inverter-fed induction motor drive system, which can not only satisfy the requirements for the system performance but also minimize the filter size.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.417-420
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• 2008

Solar electric systems have very little impact on environment, making them one of the cleanest power-generating technologies available. While they are operating, PV systems produce no air pollution, hazardous waste, or noise, and they require no transportable fuels. In PV system design, the selection and proper installation of appropriately-sized components directly affect system reliability, lifetime, and initial cost. In this research, we have studied the PWM(Pulse Width Modulation) signals. I proposed an efficient photovoltaic power interface circuit incorporated with a DC-DC converter and a sine-pwm control method full-bridge inverter. In grid-connected solar power systems, the DC-DC converter operates at high switching frequency to make the output current a sine wave, whereas the full-bridge inverter operates at low switching frequency which is determined by the ac frequency. Thus, it can reduce the switching losses incurred by the full-bridge inverter. Full-bridge converter is controlled by using microprocessor control method, and its operation is verified through computer aided simulations.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.670-673
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• 2000

This paper describes a new inverter active inverter between a photovoltaic(PV) array and single-phase utility that avoid the bulky input(60Hz) transformer on the AC side. The interface employs a pwm boost converter on the DC side followed by a pwm boost converter on the DC side followed by a pwm current-forced single-phase rectifier for injecting the power from the PV array into the mains. The current waveform at the AC side remains sinusoidal and exactly in phase at all time. The circuit also has the advantage of requiring fewer switching device than high-frequency link system. This paper describes modeling of PV array and new system topology. Simulation results on the performance of the connection are also presented.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.186-190
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• 2000

This paper propose a "Active common-mode voltage damper circuit" that capable of a suppression of a common-mode voltage produced in the PWM VSI. The four level half-bridge PWM inverter circuit and common-mode transformer are incorporated into the "Active common-mode voltage damper" the design method of which is presented Effect of "Active common-mode voltage damper" in this paper verifies a propriety and effectiveness in 2.2[kW] induction motor drive using IGBT inverter. Experimental results show that "common-mode voltage damper" makes contributions to reducing a high frequency leakage current and common-mode voltage.leakage current and common-mode voltage.

• Journal of Power Electronics
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• v.14 no.2
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• pp.302-314
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• 2014

Due to advancements in power electronics and inverter topologies, the current controlled multilevel voltage-source pulse width modulated (PWM) inverter is usually preferred for accurate control, quick response and high dynamic performance. A multilevel topology approach is found to be best suited for overcoming many problems arising from the use of high power converters. This paper presents a comprehensive review and comparative study of several current control (CC) techniques for multilevel inverters with a special emphasis on various approaches of the hysteresis current controller. Since the hysteresis CC technique poses a problem of variable switching frequency, a ramp-comparator controller and a predictive controller to attain constant switching frequency are described along with its quantitative comparison. Furthermore, various methods have been reviewed to achieve hysteresis current control PWM with constant switching frequency operation. This paper complies various guidelines to choose a particular method suitable for application at a given power level, switching frequency and dynamic response.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.2
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• pp.173-183
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• 2014

In this paper, an analysis of power losses for the three-level T-type and neutral-point clamped (NPC) PWM inverters is presented, in which the conduction and switching losses of semiconductor devices of the inverters are taken into account. In the inverter operation, the conduction loss depends on the modulation index (MI) and power factor (PF), whereas the switching loss depends on the switching frequency. Power losses for the T-type and NPC inverters are analyzed and calculated at the different operating points of MI, PF and the switching frequency, in which the four different models of semiconductor devices are adopted. In the case of lower MI, the NPC-type is more efficient than the T-type, and vice versa. The validity of the power loss analysis has been verified by the simulation results.

• Proceedings of the KIEE Conference
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• 1999.11a
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• pp.56-60
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• 1999

This paper presents the high performance real time control system of PWM inverter for uninterruptible power supply(UPS). This system is based on a digital control scheme which calculates the pulse widths of the inverter switches for the next sampling time in digital signal processor(DSP). A PI compensator is used to eliminate the voltage error caused by the difference between the actual values of LC filter and those designed. Double regulation loops which are the inner current loop and the outer voltage loop are used to make the transient response time reduce in load disturbance and nonlinear load. This method makes it possible to obtain better response in comparison to conventional digital control system. The proposed scheme provides good performance such as stable operation, low THD of the output voltage, and good dynamic response for load variations and nonlinear load.

• Journal of IKEEE
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• v.23 no.4
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• pp.1182-1186
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• 2019

This paper discussed the research results on the development and output characteristics of single-phase direct drive 20W BLDC motor with ADC converter. It is designed to drive the rotor through PWM inverter switching and position the back electromotive force of the motor electrically 30° ahead of the hall sensor phase angle signal to ensure optimum switching time. As a major result of the characteristics evaluation, the maximum inverter efficiency was 92[%], the system efficiency was 53.34[%,] and the motor efficiency was 57.85[%].

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.281-283
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• 1995

Deadbeat controlled PWM Inverter is realized. This PWM inverter performs the instantaneous control method which is based on the real-time digital feedback control and the microprocessor-based deadbeat control. For the deadbeat current controller, the system's order becomes a high order and increases computation delay time. Therefore, The delay tine produces current ripple. To minimize the current ripple, a new method based on deadbeat control theory for current regulation is proposed. It is constructed by a reduced-order state observer which predicts the output current in next sampling instant.