• Journal of Advanced Navigation Technology
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• v.27 no.2
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• pp.197-202
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• 2023

This paper presents the design method and electrical characteristics of a high-efficiency power amplifier for a 50 Watts class repeater applied to a 5G system and used in in-building, subway, and tunnel. GaN was used for the termination transistor of the power amplifier designed here, and intermodulation signals were removed using DPD to satisfy linearity. In addition, in order to handle various requirements such as amplifier gain control and alarm processing required in the 5G system, the microprocessor is designed to exist inside the power amplifier. The amplifier manufactured to confirm the electrical performance of the power amplifier satisfying these conditions satisfied 46.5 dBm and the overall efficiency of the amplifier was 37%, and it was confirmed that it satisfied various alarm conditions and electrical characteristics required by telecommunication companies.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.377-380
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• 2000

In this paper, a new adaptive linearizer architecture with the predistorter is proposed. In the M.Ghaderi's paper, two analog predistorters and an envelope detector are used. Analog circuits for the analog predistorter and the envelope detector can cause imperfection and inaccuracy of the system and make circuits more complex. To solve those problems, most of processes including the predistortion are made by the DSP. The RLS algorithm is applied so that the errors between power amplifier output signals through the postdistorters and predistorted input signals can be converged to the global minimum.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.77-78
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• 2005

In this paper, Compact Microstrip Resonants Cell(CMRC) have been employed to suppress IMD(Intermodulation Distortion) of the 3-Way Doherty amplifier. This method can not only improve the linearly and the efficiency but also is simpler, smaller and more inexpensive than existing linearly methods; (for example Harmonic feedback, Back off, Feed-forward, Predistortion and so on.) Also, the proposed 3-way Doherty amplifier using only one divider has been reduced size of existing 3-Way Doherty amplifier. As a result, the proposed Doherty amplifier using CMRC and only one divider has been improved for the IMD$_3$ by 4.474dBc, and the PAE by 9.199%, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.9-15
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• 1994

In this paper, the linearized power amplifier using digital adaptive predistorter is implemented in order to restrict spectral spreading and adjacent channel interference. The linearized systems is composed of a DSP56001 processor that executes predistortion in baseband. 90.deg. phase shifter, power splitter/combiner, quadrature modulator/demodulator of 360MHz band, and nonlinear amplifier. A ${\pi}$/4-shift QPSK is used to modulate digital random signals. As the quantized power of baseband signal and the output of amplifier are fed to the predistorter, and predistorting values are calculated using an adaptive algorithm. In the experiment, a peak to sidelobe ratio of the linearized amplifier is improved up to 15dB in comparison with conventional nonlinear amplifier, which means that the distortion of transmitted signal is decreased and adjacent channel interference was reduced.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.182-185
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• 2002

A RE predistorted asymmetric Doherty amplifier for CDMA IS-95 signal has been fabricated using GaAs FETs. The Doherty amplifier used a Class AB main device and a Class C auxiliary device. At 6 ㏈ back-of from Pl ㏈ of 34 ㏈m, PAE of 27% was measured. This Doherty amplifier has higher PAE than Class AB for over 20 dB range of pout power. A RF predistortion linearizer is applied to the Doherty amplifier to improve the IMD cancellation performance. The 3rd order IMD cancellation of 12.2 ㏈ was achieved at output power of 18 ㏈m.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.393-396
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• 2001

In this paper, a new type of linearizer using a parallel diode with a bias feed resistance has been studied. It has positive gain and negative phase deviations because of a nonlinearity of the diode and movement of bias point cause by a voltage drop at the bias feed resistance. This predistortion linearizer consists of the little component and miniaturizes circuit design. The characteristics of this linearizer can be easily tuned using input bias voltage. In fabricated linearizer, maximum gain and Phase deviation of the linearizer is 1dB, 21$^{\circ}$ respectively. By applying its characteristics to the power amplifier, it will be linearized power amplifier.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.211-212
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• 2006

This paper represents a Doherty amplifier with analog predistorter to improve the linearity of the Doherty amplifier while preserving the high efficiency. A $3^{rd}$-order predistorter cancels $5^{th}$-order intermodulation (IM5) as well as $3^{rd}$-order intermodulation (IM3) components by their same phase difference in the predistorter and Doherty amplifier. This is accomplished by independently controlling their phase by using the phase-controlled error generator in the predistorter. For experimental verification, a $3^{rd}$-order predistorter has been implemented and tested in a 180-W Doherty amplifier at the wide-band code division multiple access (WCDMA) band. The measured results show good performance with the predistortion Doherty amplifier.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.273-276
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• 2003

In this paper, we designed and made up/down converter (UDC) for using W-CDMA digital pre-distortion system which is one of the efficiency enhancement techniques. UDC is required that frequency up(baseband to RF) and down(RF to baseband) of information signals. The focus of the design and PCB layout is to satisfy the linearity of the UDC. We tested that UDC was satisfied specification which is based on 3GPP base stations and repeaters. The ACLR results which are -51.84dBc(Up Converter) and -55.0dBc(Down Converter) at upper 5 MHz offset from center-frequency show that UDC satisfy the 3GPP specification with superior linearity data.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.8
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• pp.1428-1436
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• 2000

An adaptive predistorter linearizer suitable for the DSP implementation is proposed. Predistortion is performed by the DSP instead of the analog predistorter. RLS algorithm is employed for the optimization process to minimize the errors between the predistorter and postdistorter output signals. Computer simulation results for our linearizer show good performance.

• Journal of electromagnetic engineering and science
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• v.8 no.1
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• pp.17-22
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• 2008

It is presented that sampling rates for behavioral modeling of quasi-memory less nonlinear devices can be far less than the Nyquist rate of the input signal. Although it has been believed that the sampling rate of nonlinear device modeling should be at least the Nyquist rate of the output signal, this paper suggests that far less than the Nyquist rate of the input signal can be applied to the modeling of quasi-memoryless nonlinear devices, such as frequency multipliers. To verify, a QPSK signal at 820 MHz were applied to a frequency tripler, whereby the device can be utilized as an up-converting mixer into 2.46 GHz with the aid of digital predistortion. AM-AM, AM-PM and PM-PM can be successfully measured regardless of sampling rates.