• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.1-6
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• 2011

This paper describes a phase modulation I/O (PMIO) serial interface circuit that supports 1Gbps transfer rate with 12mW power consumption at 1.2V supply. The proposed PMIO which consists of TX and RX blocks utilizes a phase modulation technique. The rising edge is fixed to get the clock phase information and falling edge has multi positions for the multi-data information to increase the transfer rate. The designed circuit use the 16 possible falling edge positions. The data transfer rate is four times faster than the clock rate. The circuit has been implemented using $0.13{\mu}m$ CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of transfer data (phase data) and recovery data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.5
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• pp.37-42
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• 2012

In this paper, a new charge pump is proposed to reduce the timing mismatch in the conventional current-steering charge pumps. Conventional current-steering charge pumps used NMOS input stages both for UP and DOWN signals, which resulted in different numbers of stage for UP and DOWN delay paths. The proposed charge pump has equalized the numbers of stages for UP and DOWN signals by using a PMOS stage for the DOWN signal. The simulation results show that the conventional current-steering charge pump has 14ns and 6ns for optimized timing mismatches between UP and DOWN signals for turn-on and turn-off, respectively. On the other hand, the proposed charge pump has improved timing mismatches of 6ns and 5ns for turn-on and turn-off, respectively. As a result, the reference spurs are reduced from -26dBc to -39dBc for the proposed charge pump. The proposed charge pump was designed by using $0.18{\mu}m$ CMOS technology. The measurement results show that the maximum variation of the charging and discharging current over the charge pump output voltage range of 0.3~1.5V is approximately 1.5%.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.24-30
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• 2007

In this paper, an energy detection-based low power, low complexity IR-UWB receiver in multipath impulse radio channel is presented. The proposed receiver has a simple 1-bit sampler for energy detection. Also, multipath signal received from multipath impulse radio channel is amplified and envelope of the signal is detected. Then, energy detection technique using integrator by summing multipath signals in certain period is adopted to minimize the BER loss by simple energy detection. In particular, in acquisition of a sample signal, SNR is additionally improved using a digital sampler. Symbol decision using several sampled signals is performed and thus the process of symbol synchronization is significantly simplified. Also, it is effectively designed to be compatible with influences of multipath and timing error. In addition, the proposed receiver complexity is reduced using pulse decision window. The performance of the proposed receiver is simulated based on IEEE 802.15.4a channel model and the algorithms are implemented on FPGA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.107-113
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• 2014

A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.

• Korean Journal of Optics and Photonics
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• v.16 no.1
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• pp.21-26
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• 2005

10 GHz clock recovery from 40 Gbit/s optical time-division-multiplexed(OTDM) signal pulses was experimentally demonstrated using an optical phase lock loop based on a terahertz optical asymmetric demultiplexer(TOAD) with a local-reference-oscillator-free electronic feedback circuit. The 10 GHz clock was successfully extracted from 40 Gbit/s signals. The SNR of the time-extracted 10 GHz RF signal to the side components was larger than 40 dB. Also we performed numerical simulation about the extraction process of phase information in TOAD. The lock-in frequency range of the clock recovery is found to be 10 kHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.10 s.89
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• pp.952-960
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• 2004

PSK(Phase Shift Keying) is useful because of the power and spectral efficient modulation. In this paper, no additional hardware will be needed to support various transmit mode in the suggested DSP scheme. We design and implement the synchronization algorithm for M-ary PSK(M=2, 4) demodulator based on DSP scheme, instead of complex analog PSK demodulator. TMS320C6203 is used as DSP. We check the all kinds of waveforms via the graph view window after software programming the emulation on the DSP tool. The result of implementation proves that demodulator using the suggested algorithm has equal performance with demodulator using analog circuits.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.501-512
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• 2018

Radio frequency identification (RFID) sensor tag provides several advantages including battery-less operation and low cost, which are suitable for long-term monitoring. This paper presents a self-powered RFID temperature sensor tag for online temperature monitoring in substation. The proposed sensor tag is used to measure and process the temperature of high voltage equipments in substation, and then wireless deliver the data. The proposed temperature sensor employs a novel phased-locked loop (PLL)-based architecture and can convert the temperature sensor in frequency domain without a reference clock, which can significantly improve the temperature accuracy. A two-stage rectifier adopts a series of auxiliary floating rectifier to boost its gate voltage for higher power conversion efficiency. The sensor tag chip was fabricated in TSMC $0.18{\mu}m$ 1P6M CMOS process. The measurement results show that the proposed temperature sensor tag achieve a resolution of $0.15^{\circ}C$/LSB and a temperature error of $-0.6/0.7^{\circ}C$ within the range from $-30^{\circ}C$ to $70^{\circ}C$. The proposed sensor tag achieves maximum communication distance of 11.8 m.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.1
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• pp.94-102
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• 2003

This paper describes the load parallel type full-bridge high frequency resonant inverter can be used as power source. Output control method of proposed circuit is compared with pulse frequency modulation(PFM), pulse width modulation(PWM) and pulse phase variation(Phase-Shift). The analysis of the proposed circuit is generally described by using the normalized parameters. The principle of basic operating and the its characteristics are estimated according to the parameters such as switching frequency(${\mu}$), pulse width($\theta$d) the variation of phase angle($\phi$) by three driving signal patterns. Experimental results are presented to verify the theoretical analysis result. In future, Characteristics by three driving signal control method is provided as useful data in case of output control of a power supply in various fields as induction heating application, DC-DC converter etc.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1038-1044
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• 2011

In this paper, the multichannel intermediate frequency transceiver for broadband multimedia system is designed and the experimental results are analyzed. Basic elements of the transceiver such as frequency synthesizer, amplifier, mixer, automatic gain control amplifier are introduced. The analysis technique described here applies not only to amplifier but also to any other nonlinear components such as mixers and frequency doubler. Through the investigation of the power spectrum density of the transmitted signal, the phase noise of the local oscillator is evaluated below 70 dBc/kHz. The frequency characteristics of the modulated signal is flat within the system bandwidth. Also the effects of adjacent channel interference and supurious emission are analyzed. And the function of automatic gain control amplifier is well operated.